Key code data generator

ABSTRACT

Key switches are connected in a matrix fashion between row lines making block lines for octaves and column lines making note lines for notes. The note lines are connected to a note detection circuit which converts the note line outputs of the actuated switches into key codes in a time shared fashion and to a chord detection circuit which includes a chord type detecting logic and a shift register connected thereto and storing the note line outputs in its respective stages. During a chord detecting period, the note detection circuit is loaded with signals &#34;1&#34; as if all the key switches were actuated and delivers key codes of all notes one after another, whereas the shift register is circulatingly shifted synchronously with the note code change. When the logic detects an establishment of a chord, the note code of that moment is extracted to be a code identifying the root note of the chord. The root note code is then processed for automatic bass and chord performance.

BACKGROUND OF THE INVENTION

This invention relates to a key code data generator capable of detectingswitches in operation among a number of key switches and functionswitches and generating key code data for an automatic bass chordperformance on the basis of signals from the detected switches.

The specification of U.S. Pat. No. 4,148,017 to the same assigneediscloses a key code data generator which detects an on (or off) stateof a key switch among a large number of key switches provided on akeyboard of an electronic musical instrument and generates key code datarepresentative of a depressed key in accordance with a result ofdetection. The specification of U.S. patent application No. 825,443 tothe same assignee also discloses a key code data generator whichgenerates key code data to be utilized for an automatic bass performanceand an automatic chord performance from key code data representing adepressed key.

Simplification of circuitry and reduction of the number of pins whichconstitute input and output terminals are major problems to be solved indesigning a key code data generator in an integrated circuitconfiguration.

In the prior art key code data generator disclosed in the U.S. Pat. No.4,148,017 the key switches are divided into blocks and also grouped byeach note name in the respective blocks, and are arranged in a matrixfashion, respective blocks are scanned by a block detection circuit andrespective note name groups are scanned by a note detection circuit fordetection of a key switch in operation. This arrangement hasconsiderably reduced the number of required input and output lines. Theelectronic musical instrument employing this prior art key code datagenerator, however, still requires many signal lines for transmittingsignals from a number of function switches if the electronic musicalinstrument has various performance functions such as the automaticbass/chord performance and the automatic arpeggio performance.Accordingly, this prior art generator is not sufficient for theinstrument in respect of the number of signal lines.

The electronic musical instrument proposed in U.S. patent applicationNo. 825,443 detects an on or off state of key switches and functionswitches, generates key codes representing key switches which are on andgenerates key code data for the automatic bass chord performance byutilizing signals obtained by decoding these key codes. The constructionof this circuit is fairly complicated and it will be difficult to designthis circuit in an integrated circuit configuration using only one chip.

SUMMARY OF THE INVENTION

It is, therefore, a main object of the present invention to utilize thenote detection circuit for the regular note performance and also fordetection of the chord being played and delivery of the note code whichdesignates the root note of the chord to be performed.

It is another object of the invention to reduce the number of input andoutput lines of function switches by detecting an on (or off) state ofkey switches and function switches by one and the same scanningoperation.

It is still another object of the invention to provide a simplifiedcircuit by utilizing signals representing key switches which are ondetected upon scanning of the key switches for forming key code data forthe automatic bass chord performance.

In the key code data generator according to the present invention, keyswitches are divided into blocks (e.g. blocks representing octaves) andkey switches in the respective blocks are grouped by each note name.Function switches are divided into one or more blocks and functionswitches in each of the blocks are grouped in said each note name. Thusthe switches are arranged in a matrix fashion.

Blocks including a key switch or a function switch which is in an onstate are detected by a block detection circuit at a certain timing.Then, one of the detected blocks is extracted at a next timing and asignal representing the key switch or function switch which is on in theextracted block is produced.

A next one of the detected blocks is extracted and a signal representingthe key switch or function switch which is on in this block is produced.In this manner, key switches and function switches which are on aresuccessively detected in one and the same scanning operation.

In the key code data generator according to the invention, a signal isdelivered from a control circuit provided in the block detection circuitto a note detection circuit at a predetermined timing relating toextraction of the detected blocks (e.g. at a time when extraction of allof the detected blocks has been completed) and, in response to thissignal from the note detection circuit, the note detection circuitsuccessively delivers out signals representing the detected notes. Keycode data for the automatic bass performance and key code data for theautomatic chord performance are produced on the basis of the signalsdelivered from the note detection circuit. By this arrangement, theoutput of the note detection circuit is directly used for detecting aroot note for the automatic bass performance etc. whereby a circuitconstruction is considerably simplified.

These and other features of the present invention will become apparentfrom the description made hereinbelow in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram schematically showing the key code datagenerator made according to the present invention;

FIG. 2 is a diagram for explaining symbols used in circuits appearing insubsequent figures;

FIG. 3 is a circuit diagram showing an example of connections of keyswitches and functions switches;

FIGS. 4 through 6 and FIGS. 8 through 12 are circuit diagrams showing indetail an embodiment of the key code data generator according to theinvention in which FIG. 4 shows a block detection circuit, FIG. 5 a notedetection circuit, FIG. 6 a state control circuit, FIG. 8 control signalforming circuit, FIG. 9 a chord memory and a function data transmissioncircuit, FIG. 11 a key code register and key code processing circuit andFIG. 12 a generation circuit respectively;

FIG. 12 is a time chart for explaining the operations of the blockdetection circuit and the note detection circuit;

FIG. 13 is a time chart for explaining the operation of the functiondata transmission circuit; and

FIG. 14 is a time chart for explaining the operation of the chorddetection circuit.

DESCRIPTION OF A PREFERRED EMBODIMENT

1. General description of the overall construction

FIG. 1 schematically shows a preferred embodiment of the key code datagenerator according to the invention. Key switches and function switches1 are divided into a plurality of blocks whereas the key switches in therespective blocks are grouped note by note and the function switches inthe respective blocks are grouped in accordance with some selectednotes. The key switches and the function switches belonging to the sameblock are commonly connected and those belonging to the same note arealso commonly connected. The common connection lines for the respectiveblocks are designated as block lines bn and the common connection linesfor the respective notes as note lines nn. Alternatively stated, the keyswitches and the function switches are disposed in a matrix circuitconsisting of the block lines bn arranged as rows and the note lines nnarranged as columns so that a key switch or function switch which is oncan be identified by signals delivered on specific ones of the blocklines bn and the note lines nn.

A block detection circuit 2 detects, from the signal delivered on theblock line bn, a block to which the key switch or function switch whichis on belongs. The block detection circuit has storage positionscorresponding to the respective blocks, a storage position for anautomatic bass/chord processing and a storage position for an automaticarpeggio processing. A note detection circuit 4 detects, from the signaldelivered on the note line nn, the note of the key switch or functionswitch which is on. The note detection circuit 4 has storage positionscorresponding to the respective notes (i.e. notenames). The operationsof the block detection circuit 2 and the note detection circuit 4 arecontrolled by successively carrying out four detection operation states,S₀, S₁, S₂, and S₃. The first operation state S₀ is a stand-by state. Inthe second operation state S₁, a signal is transmitted from the notedetection circuit 4 to the block detection circuit 2 through the keyswitches and function switches which are on to detect all blocks towhich the switches which are on belong at once and cause these blocks tobe stored in the respective corresponding storage positions. In thisoperation state, a signal is also stored in the storage positions forthe automatic bass/chord processing and the automatic arpeggioprocessing.

As the operation state proceeds to the state S₂, one of the signalsstored in the storage positions of the block detection circuit 2 isextracted and delivered out. The extraction of this single signal isconducted in a certain order of precedence. In this embodiment, priorityis given in the order of a block including a function switch, a blockincluding a key switch of pedal keyboard, a block including a key switchof a lower keyboard, a block including a key switch of an upperkeyboard, the automatic bass/chord processing and lastly the automaticarpeggio processing. No signal is extracted from any of these storagepositions while a signal remains stored in a storage position which isof a higher priority order. When a signal is outputted from the storageposition of the highest priority in the block detection circuit 2, asignal is simultaneously transmitted from the block detection circuit 2to the note detection circuit 4 through the block line corresponding tothe particular storage position and the key switches or the functionswitch which is on in that block, thereby causing all notescorresponding to the key switches or the function switch which is on tobe detected at once and signals representing these notes to be stored intheir respective note storage positions.

As the operation state proceeds to the state S₃, the signals stored inthe storage positions of the note detection circuit 4 are delivered outone by one in accordance with a certain order of precedence. In thiscase, priority is given from the lower tone side and as a signal isoutputted one by one, the storage position from which the signal hasbeen outputted is cleared. Upon outputting of all of the signals storedin the storage positions of the note detection circuit 4, the operationstate returns to the state S₂ and a signal is extracted from a storageposition corresponding to a block of a next priority in the blockdetection circuit 2. This signal is transmitted to the note detectioncircuit 4 through a block line corresponding to the storage position ofthe signal and notes of key switches or a function switch which is on inthe block thereby are detected. Signals representing the detected notesare successively outputted in the next operation state S₃. In thismanner, the states S₂ and S₃ are repeated. Upon completion of extractionof the blocks detected in the state S₁ and outputting of signalsrepresenting blocks and notes corresponding to the key switches andfunction switches which are on, an automatic bass/chord control signalAP is outputted in the state S₂ from the storage position for theautomatic bass/chord processing. This signal AP is applied to therespective storage positions of the note detection circuit 4 so that asignal "1" is stored in all of the storage positions. In the next stateS₃, signals representing respective notes are successively outputtedfrom their respective storage positions in the note detection circuit 4with priority being given in the lower tone side. These signals are usedfor detecting a root note in the automatic base performance and theautomatic chord performance, as will be described later. As the signalAP has been outputted from the storage position for the automaticbass/chord processing in the block detection circuit 2 and the storageposition has been cleared, a signal is then outputted from the storageposition for the automatic arpeggio processing. This output from thestorage position for the automatic arpeggio processing is not applied tothe note detection circuit 4 but serves only to secure a unit operationtime (i.e., the period of the clock pulse used for the system) for theautomatic arpeggio processing.

When the automatic arpeggio processing time has elapsed, the storagepositions of the block detection circuit 2 have all been cleared and theoperation state returns to the initial state, i.e., the stand-by stateS₀. Upon detection of this stand-by state S₀, the operation states S₁-S₃ are carried out again and detection of all the key switches andfunction switches in operation is repeated.

In the above described manner, detection of blocks including keyswitches or function switches which are on are carried out in the blockdetection circuit 2 whereas detection of notes corresponding to the keyswitches or function switches which are on in the detected blocks iscarried out in the note detection circuit 4.

The block detection circuit 2 outputs, in response to each extraction ofthe block, a block type code BC representing the type of the functionblock, type of the keyboard and whether the storage position for theautomatic bass/chord processing has been extracted or not and alsoproduces an octave code OC representing the octave of the detected keyswitch. The note detection circuit 4 outputs a note code NC representingthe note of the detected key switch. The block kind code BC outputtedfrom the block detection circuit 2 is applied to a block kind coderegister 8 and held temporarily therein. This code BC held in theregister 8 is decoded in a decoder 10 and thereafter is applied to acontrol signal forming circuit 11. The control signal forming circuit 11produces a control signal used for controlling a chord detection circuit5, a function data memory 6, a function data transmission circuit 7 anda key code register 9 to be described later.

The octave code OC outputted from the block detection circuit 2 and thenote code NC outputted from the note detection circuit 4 are applied tothe key code register 9 and held temporarily therein.

As was previously described, extraction of the block detection circuit 2is conducted with priority being given first to the block including afunction switch. Accordingly, the note detection circuit 4 firstoutputs, in parallel, signals representing function switches which areon from storage positions of the notes corresponding to the functionswitches. These signals are applied to the function data memory 6 andthe function data transmission circuit 7 through the chord detectionmemory 5. The function data memory 6 is provided for storing functiondata used in this circuit i.e., in this chip and data which is not usedin this chip is applied to the function data transmission circuit 7. Thefunction data transmission circuit 7 consists, for example, of a shiftregister and converts input parallel function data to serial data. Theconverted data outputted from the circuit 7 is applied to a control datamemory (not shown). The control data memory consists, for example, of aread-out memory and produces desired control data such as fordetermining a bass pattern in the automatic bass performance in responseto the applied function data. Detailed description of this control datamemory will be omitted for this memory is not related to the subjectmatter of the present invention.

The block detection circuit 2 subsequently extracts the blocks in theorder of the block including the key switches of the pedal keyboard, theblock including the key switches of the lower keyboard and the blockincluding the key switches of the upper keyboard. In response to theextraction, the octave code OC is produced from the block detectioncircuit 2 and the note code NC from the note detection circuit 4. Thesecodes are held temporarily in the key code register 9 and thereafter aresupplied to a channel processor (not shown) through a key codeprocessing circuit 12. The key code processing circuit 12, however, doesnot operate at this time and the key code KC stored temporarily in thekey code register 9 is transmitted to the channel processor withoutbeing processed by the processing circuit 12. To the channel processoris also applied a signal from the decoder 10. The channel processorassigns, in response to these signals, key code data designating a toneto be produced to one of channels equal in number to a maximum number oftones to be sounded simultaneously (e.g. twelve) for necessaryprocessing. As the channel processor, a circuit such as disclosed in thespecification of U.S. Pat. No. 4,114,495 or application No. 929,007,each assigned to the same assignee as the present case, employed.

The chord detection circuit 5 is provided for detecting a chord on thebasis of a key being depressed in the lower keyboard. In the presentembodiment, the lower keyboard is utilized as a keyboard for conductingthe automatic bass/chord performance. The chord detection circuit 5 hasstorage positions corresponding to the respective notes. When a blockincluding a key switch of the lower keyboard has been extracted in theblock detection circuit 2 and a signal representing the note of the keyswitch which is on has been outputted from the note detection circuit 4,this signal representing the note of the key which is being depressed inthe lower keyboard is stored in a corresponding one of the storagepositions of the chord detection circuit 5 with the aid of a load signalLL which is applied from the control signal forming circuit 11.

Upon completion of extraction of all the blocks including the functionswitches and key switches which are on by the block circuit 2 andextraction of the signal from the storage position for the automaticbass/chord processing, a shift signal SL is applied to the chorddetection circuit 5 from the control signal forming circuit 11 tosuccessively circulate signals stored in the respective storagepositions in the chord detection circuit 5 and representing the notes ofthe keys being depressed in the keyboard in the direction from thehigher note side to the lower note side. In the meanwhile, whether tonesof the depressed keys constitute the predetermined chord is detectedfrom a note interval relation between a signal in the storage positionof a last stage and signals in other storage positions of the chorddetection circuit 5. The signal corresponding to the storage position ofthe last stage at the time when the constitution of the chord has beendetected is used as a signal representing a root note in the chord.

Since a signal "1" is stored in the respective storage positions in thenote detection circuit 4 upon extraction of the storage position for theautomatic bass/chord processing, signals corresponding to the respectivenotes are successively outputted from the note detection circuit 4.These signals are synchronized with shifting of the signals loaded inthe respective storage positions of the chord detection circuit 5.Accordingly, the signal representing a note and being outputted from thenote detection circuit 4 at the time when forming of the chord has beendetected is nothing but a signal representing a root note. The note codeNC at this time is loaded in the key code register 9 in accordance witha load signal from the control signal forming circuit 11 and thereafteris applied to the key code processing circuit 12 as a note coderepresenting a root note.

The chord detection circuit 5 generates also a chord kind detectionsignal D representing the kind of the detected chord. This signal D isapplied to a subordinate note forming data generation circuit 13. Thiscircuit 13 successively produces a subordinate note forming data SDrepresenting predetermined note intervals on the basis of the chord kinddetection signal D and a signal representing a bass pattern from thepreviously described control data memory.

The key code data processing circuit 12 successively processes, inresponse to the subordinate note forming data SD supplied from thesubordinate note forming data generation circuit 13, the note code NCrepresenting the note code and being applied from the key code register9, thereby producing key codes KC corresponding to the subordinate noteshaving predetermined note intervals relative to the root note andsupplying these key codes KC to the channel processor.

2. Detailed description of the component parts

Description will now be made about construction and operation of aspecific example of the circuits composing the key code data generatorshown in FIG. 1. In this example, the key code data generatorschematically shown in FIG. 1 and the channel processor (not shown) arecombined in an integrated circuit on a single chip. Logic symbols shownin FIG. 2 are used with respect to the circuits described hereunder.Inverters are designated by symbols shown in FIG. 2(a), AND gates bythose shown in FIGS. 2(b) and 2(c), OR gates by those shown in FIGS.2(d) and 2(e) and exclusive OR gates by those shown in FIG. 2(f). Theordinary symbol shown in FIG. 2(b) or 2(d) is used for a case where thenumber of input lines is relatively small in an AND gate or an OR gateand a symbol shown in FIG. 2(c) or 2(e) is used for a case where thenumber of input lines is relatively large. In the symbol shown in FIG.2(c) or 2(e), a single input line is drawn on the input side of the ANDor OR gate several signal lines are drawn so that they will intersectthe single input line and intersections of the single input line and thesignal lines on which signals are supplied to the AND or OR gate aremarked by small circles. The example shown in FIG. 2(c) is expressed bya logic equation of Q=A. B.D and the example shown in FIG. 2(e) by alogic equation of Q=A+B+C. A delay flip-flop is graphically expressed bya symbol shown in FIG. 2(g) or 2(h). The delay flip-flop shown in FIG.2(g) which has no representation of a clock pulse is driven by a clockpulse with a period of 48 microseconds (more specifically, a two phaseclock pulse), whereas the delay flip-flop shown in FIG. 2(h) which hasrepresentation of a clock pulse φ₁ is driven by a clock pulse with aperiod of 1 microsecond (more specifically a two-phase clock pulse).

In this example, the electronic musical instrument includes a pedalkeyboard having 26 kinds of function switches and 13 keys ranging from anote C₀ of the 0 octave to a note C₁ of the first octave, a lowerkeyboard having 49 keys ranging from a note C₁ of the first octave to anote C₅ of the fifth octave and an upper keyboard having 49 keys rangingfrom a note C₂ of the second octave to a note C₆ of the sixth octave.The key switches corresponding to the respective keys of the pedalkeyboard are grouped into a block P, the key switches corresponding tothe respective keys of the lower keyboard are grouped into blocks L₁,L₂, L₃ and L₄ individually corresponding to each of the octaves and thekeys switches corresponding to the respective keys of the upper keyboardare grouped into blocks U₁, U₂, U₃ and U₄ also corresponding to each ofthe blocks. The function switches are suitably distributed to either oftwo blocks F₁ and F₂ in such a manner that each of the function switcheswill correspond to one of the note names C♯ through C. The state inwhich the function switches and the key switches are grouped into blocksis shown in the following Table 1.

                                      TABLE 1                                     __________________________________________________________________________           Notes                                                                  Block  CL  C♯                                                                   D  D♯                                                                   E   F  F♯                                                                   G  G♯                                                                   A  G♯                                                                   B C                                 __________________________________________________________________________    Function                                                                           F1                                                                              SF  FC CA M  CON EC UL DC FS UT FSS                                                                              ST                                                                              SS                                Switch                                                                             F2                                                                              BEAT                                                                              V.sub.2                                                                          V.sub.1                                                                          BV R.sub.8                                                                           R.sub.7                                                                          R.sub.6                                                                          R.sub.5                                                                          R.sub.4                                                                          R.sub.3                                                                          R.sub.2                                                                          R.sub.1                                                                         RV                                Pedal                                                                              P C.sub.L.sbsb.0                                                                    C♯.sub.0                                                             D.sub.0                                                                          D♯.sub.0                                                             E.sub.0                                                                           F.sub.0                                                                          F♯.sub.0                                                             G.sub.0                                                                          F♯.sub.0                                                             A.sub.0                                                                          A♯.sub.0                                                             B.sub.0                                                                         C.sub.1                           keyboard                                                                      Lower                                                                              L1                                                                              C.sub.L.sbsb.1                                                                    C♯.sub.1                                                             D.sub.1                                                                          D♯.sub.1                                                             E.sub.1                                                                           F.sub.1                                                                          F♯.sub.1                                                             G.sub.1                                                                          G♯.sub.1                                                             A.sub.1                                                                          A♯.sub.1                                                             B.sub.1                                                                         C.sub.2                           keyboard                                                                           L2    C♯.sub.2                                                             D.sub.2                                                                          D♯.sub.2                                                             E.sub.2                                                                           F.sub.2                                                                          F♯.sub.2                                                             G.sub.2                                                                          G♯.sub.2                                                             A.sub.2                                                                          A♯.sub.2                                                             B.sub.2                                                                         C.sub.3                                L3    C♯ .sub.3                                                            D.sub.3                                                                          D♯.sub.3                                                             E.sub.3                                                                           F.sub.3                                                                          F♯.sub.3                                                             G.sub.3                                                                          G♯.sub.3                                                             A.sub.3                                                                          A♯.sub.3                                                             B.sub.3                                                                         C.sub.4                                L4    C♯.sub.4                                                             D.sub.4                                                                          D♯.sub.4                                                             E.sub.4                                                                           F.sub.4                                                                          F♯.sub.4                                                             G.sub.4                                                                          G♯.sub.4                                                             A.sub.4                                                                          A♯.sub.4                                                             B.sub.4                                                                         C.sub.5                           Upper                                                                              Ul                                                                              C.sub.L.sbsb.2                                                                    C♯.sub.2                                                             D.sub.2                                                                          D♯.sub.2                                                             E.sub.2                                                                           F.sub.2                                                                          F♯.sub.2                                                             G.sub.2                                                                          G♯.sub.2                                                             A.sub.2                                                                          A♯.sub.2                                                             B.sub.2                                                                         C.sub.6                           keyboard                                                                           U2    C♯.sub.3                                                             D.sub.3                                                                          D♯.sub.3                                                             E.sub.3                                                                           F.sub.3                                                                          F♯.sub.3                                                             G.sub.3                                                                          G♯.sub.3                                                             A.sub.3                                                                          A♯.sub.3                                                             B.sub.3                                                                         C.sub.4                                U3    C♯.sub.4                                                             D.sub.4                                                                          D♯.sub.4                                                             E.sub.4                                                                           F.sub.4                                                                          F♯.sub.4                                                             G.sub.4                                                                          G♯.sub.4                                                             A.sub.4                                                                          A♯.sub.4                                                             B.sub.4                                                                         C.sub.5                                U4    C♯.sub.5                                                             D.sub.5                                                                          D♯.sub.5                                                             E.sub.5                                                                           F.sub.5                                                                          F♯.sub.5                                                             G.sub.5                                                                          G♯.sub.5                                                             A.sub.5                                                                          A♯.sub.5                                                             B.sub.5                                                                         C.sub.6                           __________________________________________________________________________

Reference character SF represents a signal used for selecting a singlefinger function in an automatic accompanyment function, i.e., a functionof automatically performing chord tones consisting of a plurality oftones by depressing a single key corresponding to a root note in thelower keyboard (the chord tone performing keyboard) and designating akind of chord by a suitable means, simultaneously performingautomatically bass tones corresponding to the chord tones. FC representssignal for selecting a finger function, i.e., a function of depressing aplurality of keys in the lower keyboard in the form of a chord forautomatically performing the chord tones and simultaneously performingbass tones corresponding to the chord. CA represents a signal forselecting a custom function, i.e., a function of automaticallyperforming chord tone in accordance with tones of keys depressed in theform of a chord in the lower keyboard and automatically performing basstones using a tone of a single key depressed in the pedal keyboard as aroot tone of the base tones. M represents a signal for selecting amemory function, i.e., a function of repeating an automatic performanceeven after release of depression of keys in the lower keyboard. CONrepresents a signal for selecting a constant function, i.e., a functionof maintaining the chord tones and the bass tones as sustained tones. ECrepresents an envelope control signal for selecting two types ofenvelope shapes. UL represents a coupler signal for producing tones fromthe upper keyboard and the lower keyboard simultaneously. DC representsa damping control signal for sharply attenuating levels of tones to beproduced. The signal FS is a signal supplied from a foot switch. UTrepresents a signal for selecting an up mode in the automatic arpeggioperformance in which the tone pitch of tones to be produced rises onetone after another and a turn mode in which the tone pitch repeatedlyrises and falls. FSS represents a foot switch select signal forselecting what is to be selected by the signal FS from the foot switch.ST represents a rhythm start signal for starting the automatic rhythmperformance. SS represents a signal for selecting a "synchro-start"function according to which the automatic rhythm performance device andthe automatic bass/chord performance device are started synchronously.RV represents a signal for selecting two kinds of rhythm variations. R₁through R₈ represent signal for selecting eight different rhythms, e.g.,march, waltz, swing, slow rock, jazz rock, rumba, bosa nova and samba.BV represents a signal for selecting two kinds of bass variations in theautomatic bass performance. V₁, V₂ represent signals for selectingarpeggio variation in the automatic arpeggio performance. BEATrepresents a signal for selecting two kinds of tempo.

The numbers attached to the characters representing notes of therespective key switches represent respective octaves. For instance, thesignal C♯₂ represents note C♯ in the second octave. The signals CL₀, CL₁and CL₂ represent note C is 0 octave, first octave and second octaverespectively and indicate that they are the lowest tone in therespective keyboards.

An example of connections of the function switches and key switchesgrouped into blocks is shown in FIG. 3. One terminal (a stationarycontact side) of each of the function switches and key switches of eachof the blocks F₁, F₂, P, L₁ -L₄, U₁ -U₄ is commonly connected to one ofblock lines b₁ through b₁₁, whereas the other terminal (a movablecontact side) of each of the function switches and key switchescorresponding to the same note is commonly connected through a diode toone of note lines n₁ through n₁₃. Reference character C_(b) representsconductor capacity of each of the block lines b₁ through b₁₁ and c_(n)represents conductor capacity of each of the note lines n₁ through n₁₃.Detection of the function switches and key switches is made bypositively utilizing the conductor capacities C_(b) and C_(n).

DETECTION OF THE FUNCTION SWITCHES AND KEY SWITCHES

FIG. 4 shows an example of the block detection circuit 2. FIG. 5 anexample of the note detection circuit 4 and FIG. 6 an example of thestate control circuit 3 which controls the detection operations of theblock detection circuit 2 and the note detection circuit 4.

With reference to FIG. 4, the block detection circuit 2 comprisesdetection circuits 14-1 through 14-11 corresponding to the blocks F₁,F₂, P, L₁ -L₄ and U₁ -U₄, automatic bass/chord processing circuits 15-1and 15-2, and an automatic arpeggio-processing circuit 16. Inputterminals T_(B1) through T_(B11) of the detection circuits 14-1 through14-11 are connected to the block lines b₁ through b₁₁ shown in FIG. 3.

With reference to FIG. 5, the note detection circuit 4 comprisesdetection circuit 17-1 through 17-13 corresponding to the respectivenotes C_(L) -C. Input terminals of the detection circuits 17-1 through17-13 are connected to the note lines n₁ through n₁₃ shown in FIG. 3.

In FIG. 4, the detection circuit corresponding to the block F₁ and thedetection circuit 14-11 corresponding to the block U₄ only areillustrated in detail among the detection circuits 14-1 through 14-11.It should be noted that the other detection circuits 14-2 through 14-10corresponding to the blocks F₂, P, L₁ -L₄ and U₁ -U₃ are of the sameconstruction as circuits 14-1 and 14-11. Similarly, the detectioncircuits 17-1 and 17-13 corresponding to the notes C_(L) and C only areillustrated in detail in FIG. 5, but the other detection circuits 17-2through 17-12 corresponding to the other notes C♯ through B are of thesame construction as the circuits 17-1 and 17-13 except for some slightdifference which is peculiar to the detection circuit 17-13corresponding to the note C. Throughout the detection circuits 14-1through 14-11 and 17-1 through 17-13, component elements (AND gates, ORgates etc.) of these circuits performing the same function aredesignated by the same reference characters regardless of difference inthe block or note.

The block detection circuit 2 and the note detection circuit 4 shown inFIGS. 4 and 5 are controlled by carrying out the four states S₀ -S₃produced by the state control circuit 3 shown in FIG. 6. Which one ofthe four stages S₀ -S₃ is presently being carried out is indicated bycontents of output signals Q₁ and Q₂ of flip-flops DF₆ and DF₇ providedin the state control circuit 3. The relationship between contents of thesignals Q₁ and Q₂ and the operation states S₀ -S₄ is shown in thefollowing Table 2.

                  2                                                               ______________________________________                                        State            Q.sub.1     Q.sub.2                                          ______________________________________                                        S.sub.0          0           0                                                S.sub.1          1           0                                                S.sub.2          0           1                                                S.sub.3          1           1                                                ______________________________________                                    

With reference to FIG. 6, an initial clear signal IC which is a positivepulse is applied to a terminal T_(IC). This signal IC is inverted by aninverter I₁₂ and the inverted signal "0" is applied to AND gates A₁₇through A₂₁. The initial clear signal IC is generated at a suitable timesuch as wehn the power switch is turned on and is used for once clearingthe entire system. Accordingly, the output of the AND gates A₁₇ throughA₂₁ are all turned to "0" and so are the outputs Q₁ and Q₂ of the delayflip-flops DF₆ and DF₇. The AND gates A₁₆ to which the outputs of thedelay flip-flops DF₆ and DF₇ inverted by inverters I₁₃ and I₁₄ areapplied produces a signal TT₀ which represents the state S₀. This signalTT₀ is applied to the gates of MOS type field-effect transistors(hereinafter referred to as "the transistors" ) TR₁ (FIG. 4) in thedetection circuits 14-1 through 14-11 of the block detection circuit 2to turn on all of the transistors TR₁ and thereby cause the conductorcapacities C_(b) (FIG. 3) of the block lines b₁ through b₁₁ todischarge.

The output of the AND gate A₁₆ is applied to the delay flip-flop DF₆through an OR gate OR₂₄ and the output Q₁ of the delay flip-flop DF₆rises to "1" at a timing of a next clock pulse. At this time, the outputQ₂ of the delay flip-flop DF₇ remains in the "0" level. This enables theAND gate A₁₇ which thereupon produces an output TT₁ representing thestate S₁. Simultaneously, the output Q₁ of the delay flip-flop DF₆ isapplied as a signal TT₁ +TT₃ to the gates of transistors TR₄ (FIG. 5) ofthe detection circuit 17-1 through 17-13 of the note detection circuit4. All of the transistors TR₄ thereby are turned on to supply a powerVDD to the note lines n₁ through n₁₃ via terminals T_(NL) -T_(n13). Theconductor capacities C_(n) thereby are charged. If there is a key switchor function switch which is on, the conductor capacity C_(b) of a blockline among the block lines b₁ through b_(n) including the key switch orfunction switch which is on is charged through this key switch orfunction switch. As a result, a signal "1" is provided on the blockline. (If there are plural switches which are on, signals "1" areprovided on corresponding plural block lines). This signal is applied toan AND gate A₁ of the corresponding one of the detection circuits 14-1through 14-11 via one of the input terminals T_(B1) through T_(B11) ofthe block detection circuits 2. To the other input channel of the ANDgate A₁ is applied the signal TT₁ representing the state S₁ which is theoutput of the AND gate A₁₇ of the state control circuit 3. Accordingly,the AND gate A₁ of the detection circuit corresponding to the blockincluding the key switch or function switch which is on only is enabledto provide a signal "1" to a delay flip-flop DF₁ through an OR gate OR₁.The signal TT₁ representing the state S₁ is also applied to delayflip-flop DF₂ through DF₄ of the automatic bass/chord processingcircuits 15-1 and 15-2 and the automatic arpeggio processing circuit 16via corresponding OR gates OR₃, OR₅, OR₇.

The output Q of the delay flip-flop DF₁ of the respective detectioncircuits 14-1 through 14-11 is fed back to a data input D through an ANDgate A₂ and the OR gate OR₁. The output Q of each of the delay flip-flopDF₂ and DF₃ of the automatic bass/chord processing is fed back to eachdata input D through an AND gate A₆ and an OR gate OR₃ and through anAND gate A₈ and an OR gate OR₅. Likewise, the output Q of the delayflip-flop DF₄ of the automatic arpeggio processing circuit 16 is fedback to its data input through an AND gate A₁₀ and an OR gate OR₇. Eachof the delay flip-flops DF₁, DF₂, DF₃ and DF₄ constitutes a storagecircuit. Accordingly, in the state S₁, a signal "1" is stored in thedelay flip-flop DF₁ of the detection circuit corresponding to a blockincluding a key switch or function switch which is on. No storage of asignal is made in the delay flip-flop DF₁ of the other detectioncircuits to blocks including no key switch or function switch which ison. The delay flip-flop DF₂ and DF₃ of the automatic bass/chordprocessing circuits 15-1 and 15-2 and the delay flip-flop DF₄ of theautomatic arpeggio processing circuit 16 store a signal "1"unconditionally.

The outputs of the OR gates OR₁ of the detection circuit 14-1 through14-11, the OR gates OR₃ and OR₅ of the automatic bass/chord processingcircuits 15-1 and 15-2 and the OR gate OR₇ of the automatic arpeggioprocessing circuit 16 are applied to an OR gate OR₉. The OR gate OR₉outputs an any-block signal AB which rises to the level "1" when asignal "1" is applied to any one of the delay flips DF₁, DF₂, DF₃ andDF₄ and falls to the level "0" when all of these delay flips are clearedof the signal "1". This any-block signal AB is applied to a data input Dof a delay flip-flop DF₇ through an OR gate OR₂₅ and the output Q₂ ofthe delay flip-flop DF₇ is turned to "1" at the timing of a next clockpulse. Since the output of the OR gate OR₂₄ is "0" at this time, theoutput Q₁ of the delay flip-flops DF₆ is turned to "0". The AND gate A₁₈thereby is enabled and the operation mode is changed to the state S₂.

The signal "1" stored in the delay flip-flop DF₁ of one of the detectioncircuits 14-1 through 14-11 of the block detection circuits 2corresponding to the block including the key switch or function switchwhich is on is applied to the AND gate A₃. The AND gate A₃ constitutes apriority circuit. The AND gate A₃ of the detection circuit 14-1corresponding to the block F₁ which is given a top priority isunconditionally enabled by applying a signal "1" which is obtained byinverting a signal "0" at a ground level by an inverter I₂. Each of theother detection circuits 14-2 through 14-11 receives a signal which isobtained by inverting by an inverter I₂ an output of the OR gate OR₂ towhich the output Q of the delay flip-flop DF₁ of the preceding detectioncircuit and the output of the OR gate OR₂ of the preceding detectioncircuit are applied. The AND gate A₃ in each of the detection circuits14-2 through 14-11 is enabled on condition that none of the delayflip-flops DF₁ of the detection circuits of higher priority ordersstores a signal "1". If there is storage of the signal "1" in any of thedelay flip-flops DF₁ of the detection circuits of higher priorityorders, the AND gate A₃ is disabled.

The output of the AND gate A₃ is applied to an AND gate A₄ while theoutput of the AND gate A₃ is inverted by an inverter I₃ and thereafteris applied to an AND gate A₅. The signal TT₂ representing the state S₂is applied from the AND gate 18 of the state control circuit 3 to theother inputs of the AND gates A₄ and A₅. The signals "1" stored in thedelay flip-flops DF₂ and DF₃ of the automatic bass/chord reprocessingcircuits 15-1 and 15-2 are applied to AND gates A₇ and A₉ having threeinput channels and the signal "1" stored in the delay-flop DF₄ in theautomatic arpeggio processing circuit 16 is applied to an AND gate A₁₁having three input channels. The AND gate A₇ receives at the other inputthereof a signal obtained by inverting the output of the OR gate OR₂ ofthe detection circuit 14-11 by an inverter I₅ and the signal TT₂representing the state S₂. The AND gate A₉ receives at the other inputsthereof a signal obtained by inverting by an inverter I₇ the output ofan OR gate OR₄ to which the output Q of the delay flip-flop DF₂ of theautomatic bass/chord processing circuit 15-1 and the output of the ORgate OR₂ of the preceding stage are applied and the signal TT₂representing the state S₂. The AND gate A₁₁ receives at the other inputthereof a signal obtained by inverting by an inverter I₉ the output ofan OR gate OR6 to which the output Q of the delay flip-flop DF₃ of theautomatic bass/chord processing circuit 15-2 and the output of the ORgate OR4 of the preceding stage are applied and the signal TT₂representing the state S₂. The AND gates A₇, A₉ and A₁₁ therebyconstitute a priority circuit. Accordingly, in the state S₂, a block ofthe highest priority among blocks stored in the delay flip-flop DF₁ ofthe detection circuits 14-1 through 14-11 is extracted and only the ANDgate A₄ of the detection circuit corresponding to the extracted blockoutputs a signal "1". This signal "1" is applied to the AND gate A₂through the inverter I₁ to clear the storage in the delay flip-flop DF₁and also constitutes a block detection output of this detection circuit.The output "1" of the AND gate A₄ is also applied to the gate of thetransistor TR₂ to discharge the conductor capacity C_(b) of the blockline for the extracted block. At this time, the output of the AND gatesA₃ of the other detection circuits are "0". Accordingly, the AND gate A₅is enabled to apply a signal "1" to the gate of the transistor TR₃. As aresult, the conductor capacity C_(b) of the block line for each of theblocks corresponding to the other detection circuits is charged and thediodes D (FIG. 3) connected in series to the key switches or functionswitches in the other blocks are reversely biased. Accordingly, a signal"0" is provided only on a note line to which the key switch or functionswitch which is on in the extracted block is connected, the other notelines presenting a signal "1". This signal "0" is inverted by aninverter I₁₀ in a corresponding one or ones of the detection circuits17-1 through 17-13 of the note detection circuit 4 (FIG. 5) andthereafter is applied to an AND gate A₁₂. The AND gate A₁₂ receives atthe other input thereof the signal TT₂ representing the state S₂ fromthe state control circuit 3, so that a signal "1" is applied in thestate S₂ to the data input D₅ of the delay flip-flop DF₅ via an OR gateOR₁₆ or OR₁₈. The delay flip-flop DF₅ feeds back its output Q to itsinput D via an AND gate A₁₄ and the OR gate OR₁₆ or OR₁₈ thereby forminga storage circuit. Accordingly, when the signal "1" is applied throughthe OR gate OR₁₆ or OR₁₈, this signal "1" is stored in the correspondingdelay flip-flop DF₅. The output of each of the OR gate OR₁₆ or OR₁₈ isapplied to an OR gate OR₁₉. The OR gate OR₁₉ produces an "any note"signal AN which rises to "1" upon application of a signal to any of thedelay flips DF₅ of the detection circuits 17-1 through 17-13 andmaintains the level "1" while any one of the delay flip-flops DF₅ holdsstorage of the signal. This "any note" signal AN is applied to an ANDgate A₁₉ (FIG. 6) of the state detection circuit 3. The AND gate A₁₉there is enabled to provide a signal "1" to a delay flip-flop DF₇through an OR gate OR₂₅ and also to the delay flip-flop DF₆ through theOR gate OR₂₄. Accordingly, the output Q₁, Q₂ of the delay flip-flops DF₆and DF₇ re turned to "1" at a timing of a next pulse, bringing theoperation state to the state S₃. At this time, the signal TT₁ +TT₃ isapplied to the gates of the transistor TR₄ of the detection circuits17-1 through 17-13 of the note detection circuit 4 thereby charging theconductor capacity Cn of the note line which discharged in the precedingstate S₂.

The output of each of the delay flip-flops DF₅ of the detection circuits17-1 through 17-13 of the note detection circuit 4 is applied to an ANDgate A₁₃ which forms a priority circuit. The AND gate A₁₃ of thedetection circuit 17-1 corresponding to the note C_(L) of the highestpriority is unconditionally enabled by applying a signal "1" obtained byinverting signal "0" of a ground level by an inverter I₁₁. Each of theAND gate A₁₃ of the other detection circuits 17-2 through 17-13 receivesa signal obtained by inverting by the inverter I₁₁ the output of the ORgate OR₁₇ of the preceding stage to which the output Q of the delayflip-flop DF₅ of the preceding stage and the output of the OR gate OR₁₇of the further preceding stage are applied. Each AND gate A₁₃ of thedetection circuits 17-2 through 17-13 therefore is enabled on conditionthat no storage is held in any of the delay flip-flops DF₅ which are ofhigher priority orders and disabled if there is storage of a signal "1"in any of the delay flip-flops DF₅ of the detection circuits of higherpriority orders. Accordingly, the AND gate A₁₃ is enabled from the lowertone side in accordance with the priority order and the AND gates A₁₃ ofthe detection circuits including the delay flip-flops DF₅ storing asignal "1" successively produces a signal "1". An AND gate A₁₄ of thedetection circuit 17-1 corresponding to the note C_(L) receives a signal"0" of the ground level whereas AND gates A₁₄ of the detection circuits17-2 through 17-13 corresponding to the other notes C♯-C receive theoutputs of OR gates OR₁₇ of the detection circuits 17-1 through 17-12 ofthe previous stages. Simultaneously with outputting of a signal "1" fromthe detection circuit due to enabling of the AND gate A₁₃, the AND gateA₁₄ is disabled to clear storage of the delay flip-flop DF₅ of thedetection circuit.

When the signal "1" has been outputted from all of the AND gates A₁₃ ofthe detection circuits corresponding to the delay flip-flops DF₅ inwhich the storage is made, the storage is cleared from all of the delayflips DF₅ and the any note signal AN outputted by the OR gate OR₁₉ isturned to "0". This causes the AND gate A₁₉ of the state control circuit3 to be disabled thereby finishing the state S₃. As the state S₃ hasfinished, the output Q₁ of the delay flip-flop DF₆ is turned to "0"again so that the AND gate A₁₈ is enabled on condition that theany-block signal AB is being provided by the block detection circuit 4.The operation state therefore is changed to the state S₂. The signal TT₂representing the state S₂ is applied to the block detection circuit 4for extraction of a block of a next priority order.

In the above described manner, the block detection signal is outputtedin the state S₂ from one of the detection circuits 14-1 through 14-10 ofthe block detection circuit 2 corresponding to the extracted block. Inthe state S₃, the note detection signals representing the key switchesor function switches which are on are successively outputted from thedetection circuits 17-1 through 17-13 of the note detection circuit 4.The stage S₂ and the stage S₃ are alternately repeated until storages inthe delay flips DF₁ of the detection circuits 14-1 through 14-11 of theblock detection circuit 2 are all cleared, i.e. until extraction of theblocks detected as the blocks including the key switches or functionswitches which are on in the initial state S₁ is completed.

Assume, for example, that function switches corresponding to the signalFC for selecting the finger chord function, the signal SS for selectingthe synchro-start function and the signal R₁ for selecting a rhythm arebeing actuated, the keys corresponding to the notes C_(U), E₁ and G₁ arebeing depressed in the lower keyboard and the key corresponding to thenote E₂ is being depressed. States of signals appearing in the statecontrol circuit 3, an output of the block detection circuit 2 and anoutput of the note detection circuit 4 in this case are illustrated inthe time chart shown in FIGS. 7(a) through 7(n). FIG. 7(a) shows clockpulse times t₁ through t_(n) defined by the clock pulse φ. The signal BPshown in FIG. 7(d) represents outputs of the detection circuits 14-1through 14-11 and the automatic bass/chord processing circuits 15-1 and15-2 and the automatic arpeggio processing circuit 16. The signal NPshown in FIG. 7(l) represents outputs of the detection circuits 17-1through 17-13 of the note detection circuit 4.

When the initial clear signal IC has been applied to the terminal T_(IC)of the state control circuit 3 as shown in FIG. 7(b), the outputs Q₁ andQ₂ of the delay flip-flops DF₆ and DF₇ are turned to "0" at the clockpulse time t₁ (FIGS. 7(c) and 7(d) and the signal TT₀ representing thestate S₀ is produced (FIG. 7(e). This brings the transistor TR₁ of theblock detection circuit 2 into conduction with resulting discharge ofthe conductor capacity C_(b) of the block lines b₁ -b₁₁. At the nextclock pulse time t₂, the output Q₁ of the delay flip-flop DF₆ becomes"1" and the signal TT₁ (FIG. 7(f)) and the signal TT₁ +TT₃ (FIG. 7(h))are produced. The transistors TR₄ of the note detection circuit 4 areturned on by the signal TT₁ +TT₃ resulting in charging of the conductorcapacity C_(n) of the note lines n₁ -n₁₃. The AND gates A₁ of the blockdetection circuit 2 is enabled by the signal TT₁ and a signal "1" isstored in the delay flip-flops DF₁ of the detection circuit 14-1corresponding to the block F₁ including the signal FC for selecting thefinger chord and the signal SS for selecting the synchro-start, thedetection circuit 14-2 corresponding to the block F₂ including thesignal R₁ for selecting the rhythm, the detection circuit 14-4corresponding to the block L₁ including the notes C_(LL), E₁ and G₁ ofthe lower keyboard and the detection circuit 14-8 corresponding to theblock U₁ including the note E₂ of the upper keyboard. The signal "1" isalso stored in the delay flip-flops DF₂ and DF₃ of the automaticbass/chord processing circuits 15-1 and 15-2 and the delay flip-flop DF₄of the automatic arpeggio processing circuit 16. Simultaneously, the anyblock signal AB is produced from the block detection circuit 2 (FIG.7(i)).

At the clock pulse time t₃, the output Q₂ of the delay flip-flop DF₇ ofthe state control circuit 3 is turned to "1" whereas the output Q₁ ofthe delay flip-flop DF₆ is turned to "0" resulting in generation of thesignal TT₂ representing the state S₂ (FIG. 7(g)). This signal TT₂enables the AND gate A4 of the detection circuit 14-1 of the blockdetection circuit 2 corresponding to the block F₁. Consequently, thetransistor TR₂ is turned on with a result that the block capacity C_(b)of the block line b₁ is discharged and the block detection signal F₁ Pis produced (FIG. 7(k)). The signal TT₁ also enables the AND gate A₁₂ ofthe note detection circuit 4 to cause a signal "1" to be stored in thedelay flip-flops DF₅ of the detection circuits 17-2 and 17-3corresponding to the signals FC and SS. Simultaneously with this storageof the signal "1", the any-note signal AN outputted by the notedetection circuit 4 becomes "1" (FIG. 7(j)). At the clock pulse time t₄,the operation state is changed to the state S₃ and the signals "1"stored in the delay flip-flops DF₅ of the note detection circuit 4 aresuccessively outputted from output lines 22 and 33 corresponding to thenotes C♯ and C at clock pulse times t₄ and t₅ (FIG. 7(l)). Uponcompletion of delivery of the signal from the line 33, the any-notesignal AN becomes "0" at the clock pulse time t₅, and the output Q₁ ofthe delay flip-flop DF₆ in the state control circuit 3 is turned to "0"at the next clock pulse time t₆, bringing the operation mode to thestate S₂. In the foregoing manner, the states S₃ and S₂ are alternatelyrepeated. Signals F₂ P, L₁ P and U₁ P representing the blocks, F₂, F₁and U₁ are sequentially outputted from the block detection circuit 2and, in response thereto, the rhythm selecting signal R₁, the signalsC_(C1), E₁ and G₁ representing the notes of the lower keyboard and thesignal E₂ representing the note of the upper keyboard are sequentiallyoutputted from the note detection circuit.

As all of the signals stored in the delay flip-flops DF₁ of thedetection circuits 14-1 through 14-11 have been extracted, the AND gateA₇ of the automatic bass/chord processing circuit 15-1 is enabled in thestate S₂, producing a signal "1" as a signal A₁ P. This signal isinverted by an inverter I₄ and thereafter is applied to the AND gate A₆to disable it and thereby to clear the storage in the delay flip-flopDF₂. The output A₁ P of the automatic bass/chord processing circuit 15is applied through the OR gate OR₁₅ to the OR gates OR₁₆ of thedetection circuit 17-1 through 17-12 of the note detection circuit 4.Accordingly, a signal "1" is stored in the delay flip-flops DF₅ of thedetection circuits 17-1 through 17-12 of the note detection circuit 4when the signal A₁ P has been produced from the automatic bass/chordprocessing circuit 15-1 of the block detection circuit 2. At this time,the signal AP is not applied to the OR gate OR₁₈ of the detectioncircuit 17-13. This is for avoiding duplication since the detectioncircuit 17-1 represents the same note C as the detection circuit 17-13.The signals stored in the delay flip-flops DF₅ of the detection circuit17-1 through 17-12 of the note detection circuit 4 are successivelyoutputted from a next clock pulse time in synchronism with each blockpulse. Accordingly, a signal "1" is successively provided on the outputlines 21 through 32 of the detection circuit 17-1 through 17-12. Upongeneration of the signal "1" from the line 32 and turning of theany-note signal AN to "0", the operation state is changed to the stateS₂ and the AND gate A₉ of the automatic bass/chord processing circuit15-1 is enabled to provide a signal "1" to the AND gate A₈ through theinverter I₆ thereby to clear the storage in the delay flip-flop DF₃ andproduce the signal A₂ P. This signal A₂ P is turned to the automaticbass chord control signal AP through the OR gate OR₁₅ and applied to theOR gates OR₁₆ of the detection circuits 17-1 through 17-12 of the notedetection circuit 4 to cause the delay flip-flops DF₅ otoostore a signal"1". Accordingly, a signal "1" is successively produced on the outputlines 21 through 32 of the detection circuit 17-1 through 17-12 insynchronism with each block pulse time. This signal "1" producedsuccessively from the detection circuits 17-1 through 17-12 of the notedetection circuit 4 in response to the output A₁ P and A₂ P of theautomatic bass/chord processing circuits 15-1 and 15-2 are used fordetecting a root note for forming a key code data for the automaticbass/chord performance as will be described moreffully later.

The AND gate A₁₁ of the automatic arpeggio processing circuit 16subsequently is enabled and its output signal "1" is inverted by theinverter I₈ and thereafter is applied to the AND gate A₁₀ to clear thestorage in the delay flip-flop DF₄ and to produce the automatic arpeggiocontrol signal ARP. Upon generation of the signal ARP, the operationstate is returned to the state S₀ whereby one scanning operation by theblock detection circuit 2 and the note detection circuit 4 is completedand the same operation is repeated thereafter.

The output signals F₁ P through A₂ P of the detection circuit 14-1through 14-11 and the automatic bass/chord processing circuits 15-1 and15-2 of the block detection circuit 2 are applied to an encoder 18. Theencoder 18 consists of OR gates OR₁₀, OR₁₁ and OR₁₂ and produces signalsBC₁, BC₂ and BC which constitute a block type code. Relationship betweenthe types of blocks and the block type code BC₁ -BC₃ is shown in thefollowing Table 3:

                  TABLE 3                                                         ______________________________________                                                         Block type code                                              Block              BC.sub.3                                                                              BC.sub.2 BC.sub.1                                  ______________________________________                                        Function block                                                                             F.sub.1   0       0      1                                                    F.sub.2   0       1      0                                       Pedal keyboard                                                                             P         0       1      1                                       Lower keyboard                                                                             L         1       0      0                                       Upper keyboard                                                                             U         1       0      1                                       Automatic    A.sub.1   1       1      0                                       bass/chord   A.sub.2   1       1      1                                       processing time                                                               ______________________________________                                    

The block type code BC₁ -BC₃ generated by the encoder 18 is applied tothe block type code register 8 shown in FIG. 8

The block type code register 8 consists of 3-bit registers 8-1 through8-3 and, as is representably illustrated in detail in the register 8-3,temporarily holds, during the state S₃, the block type code BC₁ -BC₃delivered from the block detection circuit 2 in the state S₂. The blocktype code BC₁ -BC₃ is applied to the data inputs D of delay flip-flopsDF₉ through OR gates OR₂₆. The outputs Q of the delay flip-flops DF₉ arefed back to the data inputs D through AND gates A₂₃ and the OR gatesOR₂₆. The AND gates A₂₃ receive at the other inputs thereof the signalTT₃ from the state control circuit 3 (FIG. 6). This signal TT₃ is asignal obtained by delaying the output of the AND gate A₁₉ of the statecontrol circuit 3 by 48 microseconds through a delay flip-flop DF₈ andrepresenting the state S₃ as shown in FIG. 7(m).

The output signals of the block type code register 8 and signalsobtained by inverting these output signals by inverters I₁₆, I₁₇ and I₁₈are applied to the decoder 10. The decoder 10 consists of AND gates A₂₄through A₃₀ and generates from the AND gates A₂₄ through A₃₀ signals F₁T and F₂ T representing detection times of the blocks including thefunction switches, a signal PT representing detection time of the blockincluding the key switches in the pedal keyboard, a signal LTrepresenting detection time of the block including the key switches inthe lower keyboard, a signal UT representing detection time of the blockincluding the key switches in the upper keyboard and signals A₁ T and A₂T representing an automatic bass/chord processing time. These signals F₁T through A₂ T are used in the control signal forming circuit 11 (FIG.8) to be described later.

The outputs of the AND gates A₂₆ through A₂₈ of the decoder 10 aredelivered out as a signal P representing the key switch in the pedalkeyboard, a signal L representing the key switch in the lower keyboardand a signal U representing the key switch in the upper keyboard throughdelay flip-flops DF₁₂ through DF₁₄ and delay flip-flops DF₁₇ throughDF₁₉.

The output signals L₁ P through U₄ P of the detection circuits 14-4through 14-11 corresponding to the blocks L₁ through L₄ including thekey switches of the lower keyboard and the blocks U₁ through U₄including the key switches of the upper keyboard are applied to anencoder 19 consisting of OR gates OR₁₃ and OR₁₄ (FIG. 4) to be encodedinto an octave code OC₁, OC₂ representing the octave.

The outputs of the detection circuits 17-1 through 17-13 of the notedetection circuit 4 are applied to an encoder 34 consisting of OR gatesOR₂₀, OR₂₁, OR₂₂ and OR₂₃ (FIG. 5) to be encoded into a note code NC₄-NC₁ representing the note.

The octave code OC₁, OC₂ and the note code NC₁ -NC₄ are applied to thekey code register 9 shown in FIG. 11. The following Tables 4 and 5 showcontents of the octave code OC₂, OC₁ and the note code NC₄ -NC₁corresponding to the respective octaves and notes.

                  TABLE 4                                                         ______________________________________                                                       Octave code                                                    Octave           OC.sub.2   OC.sub.1                                          ______________________________________                                        1st octave       0          0                                                 2nd octave       0          1                                                 3rd octave       1          0                                                 4th octave       1          1                                                 ______________________________________                                    

                  TABLE 5                                                         ______________________________________                                                 Note code                                                            Note       NC.sub.4 NC.sub.5 NC.sub.2                                                                              NC.sub.1                                 ______________________________________                                        CL         1        1        0       0                                        C♯                                                                           0        0        0       1                                        D          0        0        1       0                                        D♯                                                                           0        0        1       1                                        E          0        1        0       1                                        F          0        1        1       0                                        F♯                                                                           0        1        1       1                                        G          1        0        1       0                                        G♯                                                                           1        0        1       0                                        A          1        0        1       1                                        A♯                                                                           1        1        0       1                                        B          1        1        1       0                                        C          1        1        1       1                                        ______________________________________                                    

PROCESSING OF SIGNALS SUPPLIED FROM THE FUNCTION SWITCHES

In the scanning of the key switches and the function switches by theblock detection circuit 2 and the note detection circuit 4, the functionswitches of the blocks F1 and F2 are first detected. Signals F₁ P and F₂P corresponding to the blocks F1 and F2 are successively outputted fromthe block detection circuit 2 and signals representing the functionswitches which are on in the blocks F1 and F2 are successively outputtedfrom the corresponding detection circuits 17-1 through 17-3 of the notedetection circuit 4. The output of the detection circuits 17-1 through17-12 of the note detection circuit 4 are applied to a note register 35of the chord detection circuit 5 shown in FIG. 9 through the lines 21through 35. The output of the detection circuit 17-13 are applied tostages 7-20 and 7-21 of a function data transmission circuit 7 through adelay flip-flop DF29 shown in FIG. 10.

The note register 35 consists of a 12-bit shift register whoserespective stages 35-1 through 35-12 are representatively illustrated indetail by the stage 35-1. Each of the stages 35-1 through 35-12comprises a load controlling AND gate A₄₈, a clear control AND gate A₄₉and a shift control AND gate A₄₇. The outputs of the AND gates A₄₇, A₄₈and A₄₉ are applied to a data input of a delay flip-flop DF₂₂ throughthe OR gate OR₂₄. The AND gate A₄₈ receives signals on the lines 21through 32 and the load signal LL. The AND gate A₄₉ receives the outputof the delay flip-flop DF₂₂ and the clear signal CL. The AND gate A₄₇receives the output of the delay flip-flops DF₂₂ of the preceding stages35-12 through 35-2 and the shift signal SL. Accordingly, the noteregister operates to load the signals on the lines 21 through 35 in thecorresponding stages 35-1 through 35-12 upon receipt of the load signalLL, clear the signals in the stages 35-1 through 35-12 upon receipt ofthe clear signal CL and successively shift the signals in the stages35-12 through 35-2 rightwardly upon receipt of the shift signal SL.

The output F₁ P (FIG. 7(k) of the block detection circuit 2 which is thefirst output of the scanning of the block detection circuit 2 and thenote detection circuit 4 is applied to an OR gate OR₃₃ of the controlsignal forming circuit 11 (FIG. 8). The output of the OR gate OR₃₃ isinverted by an inverter I₂₀ and thereafter is applied to the noteregister 35 as the clear signal CL to clear the signals in the stages35-1 through 35-12 of the note register 35. The output signal F₁ P ofthe block detection circuit 2 is applied to the block type code register8 through the encoder 18 and, after being temporarily held in theregister 8, is applied to an OR gate 34 through the AND gate A₂₄. Theoutput of the OR gate OR₃₄ is applied as the load signal LL to the noteregister 35. Accordingly, the signals including the function switcheswhich are on are successively loaded in the respective stages 35-1through 35-12 of the note register 35. Signals held in the stages 35-1through 35-10 which are a part of the signals loaded in the respectivestages of the register 35 are applied to function data memories 6-1through 6-10 (FIG. 10) via lines 41-50. The outputs of the respectivestages 35-1 through 35-12 of the note register 35 are applied to thefunction data transmission circuit 7 (FIG. 10).

The function memories 6-1 through 6-10 are provided for storing signalsSF, FC, CA, M, CON, EC, UL, DC, FS and UT from the function switches inthe block F₁ which is used in this chip. Each of these memories 6-1through 6-10 which are illustrated in detail respectively by thememories 6-1 through 6-4 comprises an AND gate A₆₁ for a clear control,an AND gate A₆₂ for a load control and a delay flip-flop DF₂₅ to whichthe outputs of the AND gates A₆₁ and A₆₂ are applied through an OR gateOR₅₁. The AND gate A₆₁ receives the output of the delay flip-flop DF₂₅and a signal obtained by inverting a load signal LF₁ to be describedlater by an inverter I₃₁. The AND gate A₆₂ receives a signal on acorresponding one of the lines 41 through 50 and the load signal LF₁.Through the memories 6-1 through 6-1, the AND gates and OR gates whichperform the same function are designated by the same referencecharacters. The memories 6-5 through 6-10 which are not illustrated indetail are of the same construction as the memory 6-4. The memory 6-1storing the signal SF used for selecting the single finger function andthe memory 6-2 storing the signal FC using for selecting the fingerchord function are somewhat different from the otehr memories 6-3through 6-10. In the memory 6-1 the AND gate 62 is inhibited by a signalobtained by inverting the signal on the line 42 by an inverter I₃₂. Inthe memory 6-2 the AND gate A₆₂ is inhibited by a signal obtained byinverting the signal on the line 43 by an inverter I₃₃.

The load signal LF₁ for controlling the function data memories 6-1through 6-10 is formed by the control signal forming circuit 11 shown inFIG. 8. Referring to FIG. 8, the output signal F₁ T of the AND gate A₂₄decoded by the decoder 10 is applied to an AND gate A₄₅. The AND gateA₄₅ receives at the other input thereof a signal TTP from the statecontrol circuit 3 shown in FIG. 6. This signal TTP is provided by theAND gate A₂₂ which receives a signal obtained by inverting the outut ofthe AND-gate A₁₉ by an inverter I₁₅ and the output of the delayflip-flop DF₈. As shown in FIG. 7(M), the signal TTP is "1" during thelast 48 microseconds of the signal TT₃ representing the state S₃.Accordingly, the AND gate A₄₅ is enabled during the last 48 microsecondsof the state S₃. The output of the AND gate A₄₅ is delayed by 48microseconds by a delay flip-flop DF₃₀ and applied to the function datamemories 6-1 through 6-10 shown in FIG. 10 as the load signal LF₁. Inthis manner, the signals representing the function switches which are onin the block F₁ are stored in the memories 6-1 through 6-10. The signalUL stored in the function data memory 6-7 is applied to the AND gate A₃₁in FIG. 8 where it is used for coupling the upper keyboard tones withthe lower keyboard tones. The function data transmission circuit 7temporarily stores required function data and transmits the data toother chips (not shown). The circuit 7 is composed of a shift registerwith 27 stages 7-1 through 7-27. In the circuit 7, AND gates, OR gates,delay flip-flops etc. in the respective stages which perform the samefunction are designated by the same reference characters. The delayflip-flops in the circuit 7 are all operated by a clock pulse φ₁ with aperiod of 1 microsecond. The stages 7-21 through 7-24 respectively storethe signals SS, ST, FSS and UT from the function switches included inthe block F₁ and their details are illustrated representatively by thestage 7-21. The respective stages 7-21 through 7-24 comprise an AND gateA₆₈ for a load control, an AND gate A₆₇ for a clear control and an ANDgate A₆₉ for a shift control. The outputs of the AND gates A₆₇, A₆₈ andA₆₉ are applied to a delay flip-flop DF₂₆ through an OR gate OR₅₄.

The stages 7-25 through 7-27 respectively store a signal FS' from thefoot switch which signal has been freed from the influence ofchattering, a key-on signal KON representing that a key switch in thepedal or lower keyboard is on and a signal ABC representing that eitherone of the single finger function, the finger chord function and thecustom function which are different modes of the automatic bass/chordfunction has been selected. These stages comprise, as representativelyshown by the stage 7-25, the load control AND gate A₆₈ and the output ofthe AND gate A₆₈ and the output of the delay flip-flop DF₂₆ of apreceding stage are applied to the delay flip-flop DF₂₆ through the ORgate OR₅₄. The foot switch signal FS' is obtained by applying the signalFS from the foot switch stored in the above described function datamemory 6-9 to a 4-bit shift register 53 through an OR gate OR₅₅ and anAND gate A₇₃ which is enabled by a pulse signal φ₀ with a pulse width of48 microseconds and a pulse period of 1 millisecond, and whenever asignal "1" is outputted from the respective bits of the shift register53, taking out this signal through an OR gate OR₅₆ thereby eliminatingthe influence of chattering. The key-on signal KON is a signaltemporarily held in the key-on register 37 (FIG. 8) as will be describedmore fully later. The automatic bass/chord selection signal ABC is asignal from an OR gate OR₅₃ which is turned to "1" if a signal "1" isstored in any one of the function data memories 6-1, 6-2 and 6-3. Thestages 7-1 through 7-7 are of a similar construction to the stages 7-25through 7-27 and comprise, as representably illustrated by the stages7-1 and 7-2, the load control AND gate A₆₈ and the output of this ANDgate A₆₈ and a signal from the delay flip-flop DF₂₆ of a preceding stageare applied to the delay flip-flop DF₂₆ through the OR gate OR₅₄. Therespective stages 7-1 through 7-7 receive a signal B from an OR gateOR₇₄ (FIG. 11) representing that the note data N₁ -N₄ and the octavedata B₁ -B₃ are generated in a circuit shown in FIG. 11 to be describedin detail later, a signal K representing that the block kind data U-ARPis generated in an OR gate OR₃₀ shown in FIG. 8 and a signal LKMrepresenting that a signal is stored in the note register 35 shown inFIG. 9. The signals applied to the stages 7-1 through 7-6 are utilizedfor testing the circuit.

The stages 7-8 through 7-20 store signals from the founction switches inthe block F₂. They comprise, as representably illustrated by the stage7-20, a load control AND gate N₆₈ a clear control AND gate A₆₇ and ashift control AND gate A₆₉. The outputs of the AND gates A₆₇, A₆₈ areapplied to a delay flip-flop DF₂₆ through an OR gate OR₅₄.

The load control AND gates A₆₈ in the respective stages 7-21 through7-27 and 7-1 through 7-7 are controlled by the outputs of AND gates A₇₁(FIG. 10). This AND gate A₇₁ receives the load signal LF₁ designatingtiming of loading of the signals to the function data memories 6-1through 6-10 and a synchronizing signal SY₃₃. As shown in FIG. 13(c),the synchronizing signal SY₃₃ is generated at the thirty-thirdmicrosecond in the clock pulse time of 48 microseconds (FIG. 13(a), FIG.7(a)) determined by the clock pulse φ. The signal SY₃₃ has a period of48 microseconds, the same as that of the clock pulse φ, and a pulsewidth of 1 microsecond. Accordingly, signals being applied to the stages7-21 through 7-27 and 7-1 through 7-7 are loaded therein at a timing ofthe synchronizing signal SY₃₃ when the signal LF₁ is being applied tothese stages.

The load control AND gates A₆₈ in the stages 7-8 through 7-20 arecontrolled by the outputs of AND gate A₇₀. The AND gate A₇₀ receives asignal LF₂ and the above described synchronizing signal SY₃₃. The signalLF₂ is formed by the control signal forming circuit 11 shown in FIG. 8.More specifically, the output of an AND gate A₄₆ enabled upon receipt ofthe signal F₂ T which is the output of the AND gate A₂₅ of the decoder10 and the signal TTP, i.e., the pulse signal outputted in the last 48microseconds of the state S₃ during which the signals representing thefunction switches which are on in the block T₂ are outputted from thenote detection circuit 4 (FIG. 5) is delayed by a delay flip-flop DF₃₁by 48 microseconds and this output of the delay flip-flop DF₃₁constitutes the signal LF₂. Accordingly, signals being applied to thestages 7-8 through 7-20 from the lines 41-52 and the delay flip-flopDF₂₉ are loaded therein at a timing of the synchronizing signal SY₃₃when the signal LF₂ is being applied to these stages.

The function data transmission circuit 7 outputs signals stored in thestages 7-1 through 7-27 from the output terminal of the delay flip-flopDF₂₆ of the stage 7-1 as a serial data signal by successively shiftingthese signals. The shift signal applied to the function datatransmission circuit 7 is formed by a flip-flop composed of NOR gatesNR₅ and NR₆. The NOR gate NR₅ receives a synchronizing signal SY₇ (FIG.13(b)) generated at the seventh microsecond of the clock pulse timedetermined by the clock pulse φ(FIG. 13(a)) while the NOR gate NR₆receives the synchronizing signal SY₃₃ (FIG. 13(c)). Accordingly, theoutput of the NOR gate NR₆ rises in synchronism with the synchronizingsignal SY₇ as shown in FIG. 13(d) and falls in synchronism with thesynchronizing signal SY₃₃. This signal is applied to the shift controlAND gate A₆₇ of the stages 7-1 through 7-27 to shift the signalssuccessively in the respective stages in a clockwise direction (i.e.,from the stage 7-27 toward the stage 7-1). These successively shiftedsignals are outputted from the delay flip-flop DF₂₆ of the stage 7-1 andis applied to the AND gate A₇₂. The AND gate A₇₂ receives at the otherinput thereof the output of the NOR gate NR₆. Accordingly, the AND gateA₇₂ outputs, during the synchronizing signals SY₇ to SY₃₃, serialfunction data FD consisting of signals LKM, BEAT, V₂, V₁, BV, R₈ -R₁,RV, SS, ST, FSS, UT, FS, KON and ABC in the order described. This signalFD is delayed by a delay flip-flop DF₂₈ by 1 microsecond, inverted by aninverter I₃₉ and thereafter is delivered from a terminal T_(FD) as afunction data FD. The outputs of the NOR gate NR₆ and the AND gate A₇₁are applied to the clear control AND gates A₆₇ of the stages 7-21through 7-24 via the NOR gate NR₄, and the outputs of the NOR gate NR₆and the AND gate A₇₀ are applied to the clear control AND gates A₆₇ ofthe stages 7-8 through 7-20 via the NOR gate NR₃ respectively forclearing the previously stored signals.

The synchronizing signal SY₃₃ is delayed by a delay flip-flop DF₂₇ by 1microsecond, inverted by an inverter I₃₉ and thereafter is delivered outas a synchronizing signal SY.

GENERATION OF KEY CODE DATA REPRESENTING THE DEPRESSED KEY

Upon extraction of the blocks F₁ and F₂ including the function switchesin the block detection circuit 2, the block P including the key switchesof the pedal keyboard is extracted and, in response thereto, the ANDgate A₂₆ of the decoder 10 (FIG. 8) is enabled to produce the signal PT.If none of the signals SF, FC and CA for selecting the automatic basschord function is generated, the output of the NOR gate NR₁ is "1" andthe AND gate A₃₄ is enabled when the signal TTP is present. This outputof the AND gate A₃₄ is applied through the OR gate OR₃₆ to the key coderegister 9-1 through 9-4 (FIG. 11) as a key data selection signal SKN.

If the blocks L₁ through L₄ including the key switches of the lowerkeyboard have been selected, the AND gate A₂₇ of the decoder 10 isenabled to produce the signal LT. If the blocks U₁ through U₄ includingthe key switches of the upper keyboard have been selected, the AND gateA₂₈ of the decoder 10 is enabled to produce the signal UT. The signal LTand UT are applied through the OR gate OR₃₆ to the key code registers9-1 through 9-4 as the key data selection signal SKN.

The key code registers 9-1 through 9-4 are provided for temporarilyholding the note code NC₁ -NC₄ generated by the note detection circuit 4(FIG. 5). Details of the key code registers 9-1 through 9-4 arerepresentatively illustrated by the register 9-1. AND gates and OR gatesperforming the same function are designated by the same referencecharacters throughout the registers 9-1 through 9-4.

The key code data selection signal SKN is applied to load control ANDgates A₇₇ of the key code registers 9-1 through 9-4 to enable these ANDgates A₇₇. The note code NC₁ -NC₄ is thereby applied to delay flip-flopsDF₃₆. The note NC₁ -NC₄ is delayed by 48 microseconds by the delayflip-flop DF₃₆ and thereafter is applied to inputs A of the adders 21-1through 12-4 via OR gates OR₆₅ through OR₆₈ while the outputs of ORgates OR₆₅ and OR₆₆ are applied to the inputs A of the adders 12-1through 12-4 via OR gates OR₇₁ and OR₂.

The key code registers 9-5 and 9-6 receive the octave codes OC₁ and OC₂generated in response to extraction of the blocks L₁ through L₄ and U₁through U₄ from the block detection circuit 2 (FIG. 4). The key coderegisters 9-5 and 9-6 temporarily hold the octave codes OC₁ and OC₂. Theregisters 9-5 and 9-6 are of the same construction and arerepresentatively shown by the register 9-5. The octave codes CO₁ and CO₂are applied to a data input D of a delay flip-flop DF₃₉ through the ORgate OR₆₂. The output Q of the delay flip-flop DF₃₉ is fed back to theinput D through an AND gate A₈₀ and the OR gate OR₆₂ and also is appliedto a delay flip-flop DF₃₈. The AND gate A₈₀ receives at the other inputthereof the signal TT₃ representing the state S₃. Accordingly, theapplied octave codes OC₁ and OC₂ are held during the state S₃.

The signal held in the key code registers 9-5 through 9-6 is a 2-bitsignal and this signal is converted to a 3-bit signal in the followingmanner. The output of the key code register 9-5 is inverted by the NORgate NR₇ and constitutes the first bit signal B₁. The outputs of the keycode registers 9-5 and 9-6 constitute the second bit signal B₂ byinputting these outputs to an exclusive OR gate ER₅. The outputs of thekey code registers 9-5 and 9-6 constitute the third bit signal byinputting these outputs to an AND gate A₉₀. Relationship between thefirst through third bit signals B₁, B₂, B₃ and the octave codes OC₁, OC₂is shown in the following Table 6.

                  TABLE 6                                                         ______________________________________                                                  OC.sub.2                                                                             OC.sub.1                                                                              B.sub.3 B.sub.2                                                                             B.sub.1                                ______________________________________                                        1st octave  0        0       0     0     1                                    2nd octave  0        1       0     1     0                                    3rd octave  1        0       0     1     1                                    4th octave  1        1       1     0     0                                    ______________________________________                                    

The first bit signal B₁ is applied to an input A of the adder 12-5 andthe second bit signal B₂ is applied to an input A of the adder 12-6.

The adders 12-1 through 12-6 add the signal applied to the input A andhte signal applied to the input B together. At this time, no signal isapplied to the inputs B of the adders 12-1 through 12-4. Accordingly,the signals applied to the adders 12-1 through 12-4 are outputted intheir original form from these adders. If, however, the outputs of thedelay code registers 9-1 through 9-4 are the note code NC₄ -NC₁ "1100"representing CL, i.e. the low tone side note C, an AND gate A₈₉ to whicha signal obtained by inverting the output of the OR gate OR₆₅ by aninverter I₄₃, a signal obtained by inverting the output of the OR gateOR₆₆ by an inverter I₄₄ and the outputs of the OR gates OR₆₇ and OR₆₈are applied is enabled to provide a signal "1" to the inputs A of theadders 12-1 and 12-2 through OR gates OR₇₁ and OR₇₂ and therebyconverting the code signal (NC₄ -NC₁) applied to the inputs A of theadders 12-1 through 12-4 to a code signal "1 1 1 1" representing C, i.e.the high tone side note C. At this time, the output "1" of the AND gateA₈₉ is applied to the inputs B of the adders 12-5 and 12-6 therebyadding "1" to the first bit signal and the second bit signalrepresenting the octave.

The outputs of the adders 12-1 through 12-2 are applied to delayflip-flops DF₄₀ and DF₄₁ through AND gates A₉₂ and A₉₃ while the outputsof the adders 12-3 and 12-4 are applied directly to delay flip-flopsDF₄₂ and DF₄₃. When the outputs of the adders 12-1 through 12-4 are"1111" representing the note C of the high tone side, the output of aNAND gate NA₁ to which the outputs of the adders 12-1 through 12-4 areapplied is turned to "0". The AND gates A₉₂ and A₉₃ are thereforedisabled and the code signal is changed to "1100" representing C_(L),i.e., the note C of the low tone side.

The outputs of the adders 12-5 and 12-6 are applied to delay flip-flopsDF₄₄ and DF₄₅ and the output of the AND gate A₉₀ is applied to a delayflip-flop DF₄₆.

In the above described manner, the delay flip-flops DF₄₀ through DF₄₃produce the note data N₁ -N₄ representing a note whereas the delayflip-flops DF₄₄ through DF₄₆ produce the octave data B₁ -B₃ representingan octave.

Assume, for example, that the note code NC₄ -NC₁ "1100" representing thenote C_(L) is loaded in the note registers 9-4 through 9-1 and theoctave code OC₂, OC₁ "0 0" representing the first octave is loaded inthe note registers 9-6 and 9-5. In this case, an AND gate A₈₄ is enabledto apply the code signal "1111" to the inputs A of the adders 12-4through 12-1 and the output "1111" of the adders 12-4 through 12-1 ischanged to the code signal "1100" again by enabling of the NAND gateNA₁. At this time, a signal "10" is applied to the inputs A of theadders 12-6 and 12-5 and a signal "11" is applied to the inputs B of theadders 12-6 and 12-5. Accordingly, the adders 12-6 and 12-5 produce anoutput "00". At this time, the output of the AND gate A₉₀ is "0" . Thedelay flip-flops DF₄₃ through DF₄₀ therefore output note data N₄ -N₁"1100" whereas the delay flip-flops DF₄₆ through DF₄₄ produce octavedata B₃ -B₁ "000". When the note code NC₄ -NC₁ representing the low toneside note C_(L) is loaded in the note register 9-1 through 9-6, the notedata N₄ -N₁ is "1100" and the octave data B₃ -B₁ is "000".

When the note code NC₄ -NC₁ "1111" representing the high tone side noteC is loaded, the NAND gate NA₁ is enabled and the note data N₄ -N₁thereupon is turned to "1100". Since, however, no signal is applied atthis time to the inputs B of the adders 12-5 and 12-6, the octave dataB₁ -B₃ representing an octave does not change. The note data N₄ -N₁ andthe octave data B₃ -B₁ constitute the key code data KC.

CHORD DETECTION

If the finger chord function (FC) or the custom function (CA) which isone mode of the automatic bass chord function is selected, the type ofchord constituted by the notes of the depressed keys in the lowerkeyboard is detected by the note interval relation between these keys.Upon extraction of the block L₁ including the key switches in the lowerkeyboard by the block detection circuit 2 (FIG. 4), a signal L1P of 48microseconds is applied to the OR gate OR₃₃ (FIG. 8). The output of theOR gate OR₃₃ is inverted by the inverter I₂₀ and applied as the clearsignal CL to the note register 35 (FIG. 9) to clear the signals held inthe respective stages 35-1 through 35-12. As the block L₁ through L₄including the key switches in the lower keyboard is extracted and, inresponse to this extraction, signals representing the notes of the keyswitches which are on are outputted from the output lines 21 through 33of the note detection circuit 4 (FIG. 5), the AND gate A₂₇ of thedecoder 10 (FIG. 8) is enabled to produce the signal LT. This signal LTis applied as the load signal LL to the note register 35 through the ORgate OR₃₄. The note register 35 loads the signals representing the notesof the key switches which are on the lower keyboard appearingsuccessively on the output lines 21 through 32 of the note detectioncircuit 4 into corresponding ones of the stages 35-1 through 35-12 forstoring these signals therein. Since the clear signal CL is generatedonly during 48 microseconds during which the signal L1P is outputtedfrom the block detection circuit 2, the note register 35 loads allsignals for the key switches which are on regardless of the blocks L₁through L₄ to which the key switches which are on belong. The outputs ofthe detection circuit 17-13 detecting the key switch corresponding tothe note C on the high tone side is loaded in the stage 35-1corresponding to the note C_(L) on the low tone side. That is to say,the output of the detection circuit 17-13 is applied to the AND gateA₁₅, The AND gate A₁₅ receives at the other input thereof a signal FTwhich is obtained by inverting by an inverter I₁₉ through an OR gateOR₃₁, the signals F₁ T and F₂ T outputted by the AND gates A₂₄ and A₂₅of the decoder 10, i.e., a signal which is "1" when blocks other thanthe blocks F₁ and F₂ including the function switches are being detected.Accordingly, the AND gate A₁₅ is enabled during detection of the keyswitches of the lower keyboard and the output of the detection circuit17-13 is applied to the load control AND gate A₄₈ in the stage 35-1 ofthe note register 35 via the AND gate A₁₅, line 20 and an OR gate OR₄₅(FIG. 9).

In the above described manner, the signals representing the notes of thekey switches which are on in the lower keyboard are loaded and stored incorresponding ones of the stages 35-1 through 35-12 in the note register35. As the extraction of the blocks including the key switches of thelower keyboard has been completed and the signal LT from the AND gateA₂₇ (FIG. 8) has disappeared, the load signal LL is turned to "0" andthe signals representing the notes of the key switches which are on inthe upper keyboard subsequently generated are not loaded in the noteregister 35.

As the extraction of the blocks including the key switches of the upperkeyboard has been completed and the signal A₁ P thereupon is outputtedfrom the automatic bass chord processing circuit 15-1, the signal A₁ Tis outputted from the AND gate A₂₉ of the decoder 10 (FIG. 8) with adelay of 48 microseconds. This signal A₁ T is applied as the shiftsignal SL to the shift control AND gate A₄₇ of the stages 35-1 through35-12 of the note register 35. Accordingly, the signal A₁ T is appliedto the note register 35 as the clear signal CL through the OR gate OR₃₃and the inverter I₂₀. The note register 35 therefore successively shiftsthe signals stored in the respective stages 35-1 through 35-12, i.e.,the signals representing the notes of the key switches which are on inthe lower keyboard, rightwardly in synchronism with the clock pulse of48 microseconds. Accordingly, the signal stored in the stage 35-12 hasbeen shifted to the stage 35-1 when 48×12 microseconds have elapsed.

In the note register 35, the signals stored in the stages 35-1 through35-12 are in predetermined note interval relations to the signal storedin the stage 35-1. More specifically the output of the stage 35-1represents a perfect prime, that of the stage 35-2 a minor seconddegree, that of the stage 35-3 a major second degree, that of the stage35-4 a minor third degree, that of the stage 35-5 a minor third degree,that of the stage 35-7 a diminished fifth degree, that of the stage 35-8a perfect fifth degree, that of the stage 35-9 a minor sixth degree,that of the stage 35-10 a major sixth degree, that of the stage 35-11 aminor seventh degree and the output of the stage 35-12 a major seventhdegree.

Accordingly, a type of chord constituted by the notes of the keysdepressed in the lower keyboard can be detected from the outputs of thestages 35-1 through 35-12 of the shift register 35 in shiftingoperation. For detecting the chord are employed a signal IN₁representing a perfect prime note which is the output of the stage 35-1,a signal IN₂ representing absence of a major second degree note andobtained by inverting the output of the stage 35-3 by an inverter I₂₇, asignal IN_(3b) representing a m minor third degree note which is theoutput of the stage 35-4 a signal IN₄ representing absence of a perfectfourth, degree note and obtained by inverting the output of the stage35-6 by an inverter I₂₆, a signal IN_(5b) representing absence of adiminished fifth degree note and obtained by inverting the output of thestage 35-7 by an inverter I₂₅, a signal IN₅ representing a diminshedfifth degree note which is the output of the stage 35-7, a signal IN₅representing a perfect fifth degree note which is the output of the35-8, a signal IN₆ representing absence of a major sixth degree note andobtained by inverting the output of the stage 35-10 by an inverter I₂₄and a signal IN₇ representing a minor seventh degree note which is theoutput of the stage 35-11. The chord detection is conducted by AND gatesA₅₂, A₅₃, A₅₄ and A₅₅.

The AND gate A₅₂ is provided for detecting a chord consisting of notesof minor seventh degree, diminished fifth degree and minor third degree.Conditions for enabling the AND gate A₅₂ is expressed by the followinglogical formula (1):

    CHH.SL.IN.sub.1.IN.sub.2.IN.sub.3♭.IN.sub.4. IN.sub.5♭.IN.sub.6. IN.sub.7♭       (1)

Alternatively stated, the AND gate A₅₂ is enabled if the keys for thenotes of prime, minor third degree, diminished fifth degree and minorseventh degree are simultaneously depressed while the keys for the notesof major second degree, perfect fourth degree and major sixth degree arenot depressed. The signal SL represent the shift signal and a signal CHHrepresents a signal obtained by inverting the output of the chorddetection signal memory 37 to be described later by an inverter I₂₈ andrepresenting that a chord has not been detected yet.

The AND gate A₅₃ is provided for detecting a chord including a minorseventh degree note (i.e., seventh chord or minor seventh chord).Conditions for enabling the AND gate A₅₃ is expressed by the followinglogical formula (2):

    CHH.SL.IN.sub.1.IN.sub.2.IN.sub.4.INH.sub.5♭.IN.sub.6.IN.sub.7.music-flat.                                                 (2)

That is, the AND gate A₅₃ is enabled if the keys for the notes of primeand minor seventh degree are simultaneously depressed while the keys forthe notes of major second degree, perfect fourth degree, diminishedfifth degree and major sixth degree are not depressed.

The AND gate A₅₄ is provided for detecting a chord including the perfectfifth degree note (major chord or minor chord). Conditions for enablingthe AND gate A₅₄ are expressed by the following logical formula (3):

    CHH.SL.IN.sub.1.IN.sub.2.IN.sub.4.IN.sub.5♭.IN.sub.5.IN.sub.6 (3)

That is, the AND gate A₅₄ is enabled if the keys for the note of primeand perfect fifth degree are simultaneously depressed while the keys forthe notes of major second degree, perfect fourth degree, diminishedfifth degree and major sixth degree are not depressed.

If either one of the above logical formulas (1), (2) and (3) issatisified during shifting of the note register 35, the OR gate OR₅₆ towhich the outputs of the AND gates A₅₂, A₅₃ and A₅₄ are applied producesa chord detection signal CH with a pulse width of 48 microseconds.

The chord detection signal CH is applied to AND gates A₅₈, A₅₉ and A₆₀to enable these AND gates. The AND gates A₅₈, A₅₉ and A₆₀ thereuponproduce signals 7b, 3b and 5b representing the type of chord. If thesignal IN₇♭ representing a minor seventh degree note is produced by thestage 35-11 when the chord detection signal CH is outputted, the ANDgate A₅₈ is enabled and an OR gate OR₄₈ thereby produces a seventhdetection signal D₇ representing a chord including a minor seventhdegree note (i.e. seventh chord). If the signal IN₃ representing a minorthird degree note if produced by the stage 35-4 when the chord detectionsignal CH is outputted, the AND gate A₅₉ is enabled and an OR gate OR₄₉thereby produces a minor detection signal Dm representing a chordincluding a minor third degree note (monor chord). If a signal isproduced by the AND gate A₅₂ when the chord detection signal CH isoutputted, the AND gate A₆₀ is enabled to produce a diminishmentdetection signal Dd representing a chord including notes of minorseventh degree, diminished fifth degree and minor third degree(diminishment chord).

The chord detection signal CH is applied to the chord detection signalmemory 37. The chord detection sig signal memory 37 applies this signalto a delay flip-flop DF₂₃ through an OR gate OR₄₃ and temporarily storesthis signal by feeding it back to the input of the delay flip-flop DF₂₃through an AND gate A₅₀ and the OR gate OR₄₃. The output of the chorddetection signal memory 37 is inverted by the inverter I₂₈ andthereafter is applied to the AND gate A₅₂ through the AND gate A₅₄. Thisarrangement is made so that once any one of the logical formulas (1),(2) and (3) has been satisfied and the chord detection signal CH hasbeen outputted during shifting of the note register 35, the AND gatesA52 through A₅₄ are disabled and outputting of the chord detectionsignal CH is prohibited even if any one of the logical formulas (1), (2)and (3) is satisfied again. In short, a chord first detected is givenpriority and no chord detection is made thereafter.

The AND gate A₅₅ is provided for generating a non-chord signal used in acase where no chord is formed. Conditions for enabling the AND gate A₅₅are expressed by the following logical formula (4):

    NCH.CHH.SL.IN.sub.1                                        (4)

The signal CHH is a signal obtained by inverting the output of thenon-chord signal memory 36 by an inverter I₂₉ and representing that thenon-chord signal N has not been generated yet.

Accordingly, the AND gate A₅₅ is enabled to produce the non-chord signalN when the signal IN₁ is first outputted from the stage 35-1 of the noteregister 35 by the shifting operation of the note register 35. Thissignal NC is applied to the non-chord signal memory 36. Upon receipt ofthe non-chord signal N, the non-chord signal memory 36 temporarilystores this signal by applying this signal to a delay flip-flop DF₂₄through an OR gate OR₄₄ and feeding back the output of the delayflip-flop DF₂₄ to the input thereof through an AND gate A₅₁ and the ORgate OR₄₄. The output NCH of the non-chord signal memory is inverted bythe inverter I₂₉ and thereafter is applied to the AND gate A₅₅. The ANDgate A₅₅ also receives a signal obtained by inverting the output CHH ofthe note detection memory 37 by the inverter I₂₈. In other words, thenon-chord signal N first outputted only is given priority.

The chord detection signal CH and the non-chord detection signal N areused for detecting a root note to be described later. However, thenon-chord signal N is not used in a case where the finger chord functionor the custom function has been selected and used only in a case wherethe single finger function has been selected.

Upon completion of one cycle of the shifting operation of the noteregister 35 by shifting of a signal from the stage 35-12 to the stage35-1, a signal A_(2p) is outputted from the automatic bass chordprocessing circuit 15-2 of the block detection circuit 2. The signalA_(2p) is inverted by an inverter I₆₀ (FIG. 9) and thereafter is appliedto the AND gate A₅₀ of the chord detection signal memory 37 to clear thestorage of the chord detection signal memory 37. The signal A_(2p) isalso used as the automatic bass chord control signal AP through the ORgate OR₁₅ (FIG. 4). This signal AP is inverted by an inverter I₃₀ andapplied to the AND gate A₅₁ of the non-chord signal memory 36 to clearthe storage of the non-chord signal memory 36.

As the signal A_(2p) is produced by the automatic bass chord processingcircuit 15-2, the AND gate A₃₀ of the decoder 10 (FIG. 8) produces asignal A_(2T). This signal A_(2T) is applied as the shift signal SL tothe note register 35 through the OR gate OR₃₂. Accordingly, signalsstored in the stages 35-1 through 35-12 of the note register 35 areshifted rightwardly again. This causes the chord detection signal CH andthe non-chord signal N to be generated in the same manner as haspreviously been described. In this case, the chord detection sigal CH isnot used but the non-chord signal N only is used for detecting a rootnote if no chord has been detected in the finger chord function orcustom function mode.

DETECTION OF A ROOT NOTE

If the finger chord function has been selected, detection of the rootnote is conducted by using the chord detection signal CH or thenon-chord detection signal N. If the signal A_(1p) is outputted from theautomatic bass chord processing circuit 15-1 of the block detectioncircuit 2 (FIG. 4), this signal A_(1p) is applied as a the signal AP tothe OR gate OR₁₆ of the detection circuit 17-1 through 17-12 of the notedetection circuit 4 (FIG. 5) through the OR gate OR₁₅. Signalsrepresenting respective notes are thereby provided on output lines 21through 32 of the detection circuit 17-1 through 17-12 (FIG. 14(3)-(14)). At this time, the shift signal SL is applied to the noteregister 35 thereby to cuccessively shift the signals stored in therespective stages 35-1 through 35-12 rightwardly. The signals aregenerated every 48 microseconds from the detection circuits 17-1 through17-12 while shifting of the note register 35 is conducted ever 48microseconds so that generation of the signals from the detectioncircuits is synchronized with shifting of the note register 35. If, forexample, a signal representing the note C♯ stored in the state 35-2 isfirst shifted to the stage 35-1 and the signal IN₁ is outputted from thestage 35-1, a signal representing the note C♯ is outputted from theoutput line 22 of the detection circuit 17-2 of the note detectioncircuit 4 in synchronization with this shifting of the signalrepresenting the note C♯. If the signal representing the note E storedin the stage 35-5 is shifted to the stage 35-1 and the signal IN₁ isoutputted from the stage 35-1, a signal representing the note E isoutputted from the output line 25 of the note detection circuit 4 insynchronization with the shifting of the signal representing the note E.Accordingly, by detecting the signal outputted from the note detectioncircuit 2 at the time when a chord has been detected, this signalrepresents a prime note, i.e., the root note.

If the output of the note register 35 satisfies either one of thelogical formulas (1), (2) and (3) and an OR gate OR₅₀ produces the chorddetection signal CH, this signal is applied to an AND gate A₃₇ of thecontrol signal forming circuit 11 (FIG. 8). The AND gate A₃₇ hasreceived at the other inputs thereof the signal FC indicating that thefinger chord function has been selected and the signal A₁ T (FIG.14(15)) indicating that the automatic bass chord processing circuit 15-1is in a processing mode. Accordingly, the AND gate A₃₇ is enabled andproduces a signal "1" upon receipt of the chord detection signal CH andthis signal "1" is applied as a root note load signal LKN to AND gatesA₇₈ of the key code registers 9-1 through 9-4 (FIG. 11) through an ORgate OR₃₈. This enables the AND gates A₇₈ to apply the note code NC₁-NC₄ outputted at this time from the encoder 34 of the note detectioncircuit 4 to delay flip-flops DF₃₇ through OR gates OR₆₁ as the rootnote. The outputs of the delay flip-flops DF₃₇ are fed back to theinputs thereof through AND gates A₇₉ and OR gates OR₆₁ so that the notecode NC₁ -NC₄ representing the root note is held in the delay flip-flopsDF₃₇. The AND gates A₇₉ receive at the other inputs thereof signalsobtained by inverting the root note load signal LKN by inverters I₄₁ soas to clear the previously stored signal representing the root note uponreceipt of the root note load signal LKN.

The output of the AND gate A₃₇ (FIG. 8) is applied to the memory 39through an OR gate OR₃₉. The memory 39 applies the signal thus suppliedto a delay flip-flop 35 through an OR gate OR₆₀ and feeds back theoutput of the delay flip-flop 35 to the input thereof through an ANDgate A₇₆ and the OR gate OR₆₀ thereby storing the applied signal.

If none of the logical formulas (1), (2) and (3) is satisfied in theshifting operation of the note register 35, the chord detection signalCH is not generated and, accordingly, the root note cannot be detected.In this case, a note represented by a signal stored in the rightmoststage among the signals stored in the note register 35 i.e., a signalfor the lowest note, is made the root note. Detection of the root notein this case is conducted by utilizing the non-chord signal NC which isdetected during shifting of the note register 35 performed again inresponse to the output A_(2p) of the automatic bass chord processingcircuit 152 (FIG. 14(2)). As the signal stored in the rightmost stage ofthe note register 35 is shifted to the stage 35-1, the AND gate A₅₅ isenabled to produce the non-chord signal N. At this time, the notedetection circuit 4 produces a signal representing the note of thesignal stored in the rightmost stage.

The non-chord signal N is applied to an AND gate 36 (FIG. 8). The ANDgate 36 receives at the other inputs thereof a signal obtained byinverting the output of the memory 39 by an inverter I₂₁, i.e., a sinalindicating that a chord has not been formed and the signal A_(2T) (FIG.14(16)) produced in accordance with the signal FC selecting the fingerchord function and the output A_(2p) of the automatic bass chordprocessing circuit 15-2. Accordingly, the AND gate A₃₆ is enabled toproduce a signal "1". This signal "1" is applied as the root note loadsignal LKN to the key code registers 9-1 through 9-4 (FIG. 11) throughthe OR gate OR₃₈. The key code NC₁ -NC₄ produced at this time by theencoder 34 of the note detection circuit 4 is the signal representingthe root note.

If the signal finger function has been selected, a note of a keydepressed in the lower keyboard is made a root note. Detection of a rootnote in this case is made by using the non-chord signal N. In the caseof the single finger function, a single key is depressed in the lowerkeyboard. Wehn a signal representing the note of this key has beenshifted to the stage 35-1 in shifting of the note register 35, thenon-chord signal N is generated. This non-chord signal N is applied toan AND gate A₃₈ (FIG. 8). The AND gate A₃₈ receives at the other inputthereof the signal SF used for selecting the single finger function andthe signal A_(1T) produced in response to the output signal A_(1p) ofthe automatic bass chord processing circuit 15-1. Accordingly, the ANDgate A₃₈ is enabled to produce a signal "1". This signal "1" is appliedto the key code registers 9-1 through 9-4 (FIG. 11) as the root noteload signal LKN via the OR gate OR₃₈. The key code register 9-1 through9-4 thereby load the note code NC₁ -NC₄ produced at this time from theencoder 34 of the note detection circuit 4 as a signal representing theroot note.

If the custom function has been selected, a note of a key depressed inthe pedal keyboard is used as a root note. As the block P including thekey switches of the pedal keyboard has been extracted by the blockdetection circuit 2 and the signal PT has been outputted by the AND gateA₂₆ (FIG. 8) of the decoder 10, this signal PT is applied to the ANDgate A₃₅. The AND gate A₃₅ receives at the other input thereof thesignal AC used for selecting the custom fucntion CA and a signal TTPwhich maintains a state "1" during the last 48 microseconds of the stateS₃. The AND gate A₃₅ therefore is enabled when a signal representing thenote of the key depressed in the pedal keyboard is outputted by the notedetection circuit 4 and produces a signal "1". This signal "1" isapplied to the key code registers 9-1 through 9-4 (FIG. 11) as the rootnote load signal LKN via the OR gate OR₃₈ for causing the note code NC₁-NC₄ being produced by the encoder 34 of the note detection circuit 4 tobe loaded as a signal representing the root note.

GENERATION OF KEY CODE DATA IN CASE WHERE THE FINGER CHORD FUNCTION HASBEEN SELECTED

If the finger chord function has been selected, the automatic chordperformance and the automatic bass performance are conducted inaccordance with plural notes of keys depressed in the lower keyboard.Key code data indicating chord notes for conducting the automatic chordperformance is produced in accordance with signals from key switches forkeys actually depressed in the lower keyboard. Key code data indicatingbass notes for conducting the automatic bass performance is produced inaccordance with the note code NC₁ -NC₄ and the octave code OC₁, OC₂representing the root note loaded in the key code registers 9-1 through9-4 (FIG. 11) and the signal D₇, D_(m) and D_(d) representing the chordtype produced by the code detection circuit (FIG. 9).

If notes of keys depressed in the lower keyboard have formed a desiredchord, the chord detection circuit 5 produces the chord detection signalCH and, in response hereto, the AND gate A₃₇ of the control signalforming circuit 11 (FIG. 8) is enabled to cause the root note loadsignal LKN to be produced from the OR gate OR₃₈. This root note loadsignal LKN is applied to the key code register 9-1 through 9-4 and alsoto a delay flip-flop DF₃₂ through an OR gate OR₅₇. The signal applied tothe delay flip-flop DF₃₂ is delayed by 48 microseconds and thereafter isapplied to an AND gate A₈₅ (FIG. 11) as a data selection signal AKD usedfor the automatic bass chord performance. The AND gate A₈₅ receives atthe other input thereof a signal T_(B) outputted by an OR gate OR₈₈which receives signals T₁, T₂, T₄ and T₈ representing a bass patternfrom a shift register 54 (FIG. 12) to be described later and the signalCON from the function data memory 6-5 (FIG. 10) indicating that aconstant function has been selected. Accordingly, the AND gate A₈₅ isenabled either when the bass pattern T₁, T₂, T₄ and T₈ is produced orwhen the constant function has been selected. The AND gate A₈₅ thereuponproduces a signal "1" and supplies it to AND gates A₈₁, A₈₂, A₈₃ and A₈₄through an OR gate OR₆₄ to enable the AND gates A₈₁ through A₈₄.

The AND gates A₈₁ through A₈₄ receive at the other input thereof theoutputs of the key code registers 9-1 through 9-4. Accordingly, the notecode NC₁ -NC₄ representing the root not loaded in the key code registers9-1 through 9-4 is applied to the inputs A of the adders 12-1 through12-4 through the AND gates A₈₁ through A₈₄ and OR gates OR₆₅ throughOR₆₈. At this time, the output AKD-TB of the AND gata A₈₅ is applied toan OR gate OR₂₉ shown in FIG. 8 to cause the delay flip-flop DF17 tooutput the signal P representing a bass tone (i.e. a tone of a key inthe pedal keyboard.

To the inputs B of the adders 12-1 through 12-4 is applied subordinatenote forming data SD₁ -SD₄. This subordinate note forming data SD₁ -SD₄representing a predetermined note interval relation to the root note isgenerated by the subordinate note data generation circuit 13 (FIG. 12).

Control data indicating a timing associated with each of various rhythmpatterns read from a control data memory (not shown) in response to thefunction data transmitted from the function data transmission circuit 7(FIG. 10) is applied in the form of an inverted serial signal PD to aterminal T_(PD). This signal PD is inverted by an inverter I₄₉ and theinverted signal PD is used to load various control data in stages 54-1through 54-17 of the shift register 54. Control data to be loaded in thestages 54-14 through 54-17 is a circuit testing signal T_(X3), T_(x2),T_(x1), T_(x0), that to be loaded in the stages 54-10 through 54-13 is a4-bit signal T₈, T₄, T₂, T₁, that to be loaded in the stages 54-8 and54-9 is chord timing signals Tc' and Tc indicating tone productiontiming of chord tones, the signal Tc' representing a signal of a longduration used for the rhythm of rhumba. Control data to be loaded in thestage 54-7 is a rhythm-on signal RHY representing that the automaticrhythm performance device (not shown) is in operation, that to be loadedin the stage 54-6 is a slow rock signal SR, that to be loaded in thestages 54-1 through 54-4 is a signal A_(r4), A_(r3), A_(r2), A_(r1)representing an arpeggio pattern. Since the arpeggio pattern signalA_(r4), A_(r3), A_(r2), A_(r1), the slow rock signal SR and the chordtiming signal Tc' are used for the automatic arpeggio performance deviceprovided in the channel processor (not shown) and not used in theillustrated circuits, detailed description of these signals will beomitted.

The outputs of the respective stages of the shift register 54 areapplied to transistors TR₁₁ through TR₂₇. The transistors TR₁₁ throughTR₂₇ are gate controlled by the output of an AND gate A₁₂₀ whichreceives a signal obtained by delaying the synchronizing signal SY₄₈ bya delay flip-flop DF₅₁ by 1 microsecond and a signal obtained by gatingthe synchronizing signal SY₄₈ by a transistor 10 with a pulse φ₁ havinga pulse width of 1 microsecond. Accordingly, the transistors TR₁₁through TR₂₇ are turned on during a first 1 microsecond of the clockpulse φ and gate out the signal loaded in the respective slages of shiftregister 54 as signals with a pulse width of 1 microsecond. This stateis held after the output of the AND gate A₁₂₀ is changed to "0".

The seventh detection signal D₇, minor detection signal D_(m) anddiminishment detection signal Dd generated by the chord detectioncircuit 5 (FIG. 9) are applied to chord memories 55-1, 55-2 and 55-3. Asrepresentably illustrated by the chord memory 55-3, each of the chordmemories 55-1 through 55-3 stores the signal applied thereto bysupplying it to a delay flip-flop DF₄₇ through an OR gate OR₇₅ andfeeding back the output of the delay flip-flop DF₄₇ to the input thereofthrough an AND gate A₉₄ and an OR gate OR₇₅. To the other input of theAND gate A₉₄ is applied a signal obtained by inverting the output ARP ofthe automatic arpeggio processing circuit 16 of the block detectioncircuit 2 by an inverter I₄₉ so that the signals stored in the chordmemories 55-1 through 55-3 are cleared each time the signal ARP isoutputted from the automatic arpeggio processing circuit 16.

The subordinate note forming data SD₁ -SD₄ is generated in response tothe signal T₁, T₂, T₃, T₄ indicating the bass pattern read from theshift register 54. The signal T₁ -T₈ is a 4-bit code signal designatinga note interval of a subordinate note relative to the root note.

As the bass pattern signal T₁ -T₈ is generated, this signal T₁ -T₈ isapplied to an AND gate A₉₇ as the signal T_(B) via an OR gate OR₈₈. Thissignal T_(B) is delayed by a delay flip-flop DF₄₉ by 48 microseconds andapplied to the other input of the AND gate A₉₇ after being inverted byan inverter I₆₁. Accordingly, the AND gate A₉₇ produces a signal "1"with a width of a 48 microseconds only when the signal T_(B) has firstbeen produced. This signal "1" is applied to an AND gate A₁₂₂ through anAND gate A₉₅, OR gate OR₇₆ and inverter I₄₇. To the other input of theAND gate A₁₂₂ is applied the output signal AKD. T_(B) of the AND gateA₈₅. Accordingly, the AND gate A₁₂₂ is enabled and supplies a signal "1"to AND gates A₁₀₀ through A₁₁₃ to enable them.

The bass pattern signal T₁, T₂, T₄, T₈ or a signal obtained by invertingthe signal T₁, T₂, T₄, T₈ by inverters I₅₈, I₅₇, I₅₆ and I₅₅ is appliedto the AND gates A₁₀₀ through A₁₁₃. Signals produced in response to thesignals D₇, D_(m) and D_(d) representing the type of a detected chordstored in the chord memories 55-1 through 55-3 are also applied to theAND gates A₁₀₀ through A₁₁₃. Accordingly, one or more of the AND gatesA₁₀₀ through A₁₁₃ are enabled and produce a signal "1" in accordancewith the bass pattern signal T₁, T₂, T₄, T₈ and the signals D₇, D_(m)and D_(d) stored in the chord memories 55-1 thorugh 55-3.

If for example, the type of the detected chord is the seventh chordincluding the minor seventh degree note and the seventh detection signalD₇ is stored in the chord memory 55-1 while no signal is stored in thechord memories 55-2 and 55-3 and if the bass pattern signal T₁, T₂, T₄,T₈ is "1000", the AND gate A₁₀₀ which receives a signal "1" produced byinverting a signal "0" supplied from the chord memory 55-2 through an ORgate OR₈₄ and the AND gate A₁₀₁ which receives only the bass patternsignal T₁, T₂, T₄, T₈ are simultaneously enabled. If the bass patternsignal T₁, T₂, T₄, T₈ is "0100", the AND gate A₁₀₂ which receives asignal produced by inverting a signal "0" supplied from the chord meory55-3 through the OR gate OR₈₃ by an inverter I₅₀ and the AND gate A₁₀₃which receives only the bass pattern signal T₁, T₂, T₄, T₈ aresimultaneously enabled. If the bass pattern signal T₁, T₂, T₄, T₈ is"1100", the AND gate A₁₀₅ which receives the output of the inverter I₅₀is enabled. If the bass pattern signal T₁, T₂, T₄, T₈ is "0010", the ANDgate A₁₀₆ which receives, through an OR gate OR₈₆ the output of aninverter I₅₀ or the output of an AND gate 121 which is enabled by theoutput of an inverter I₅₀ and the output of the chord memory 55-1supplied through an OR gate OR₈₅ is enabled. If the bass pattern signalT₁, T₂, T₃, T₄ is "1010", the AND gate A₁₀₈ which receives only the basspattern signal is enabled. If the bass pattern signal T₁, T₂, T₃, T₄ is"0110", the AND gate A₁₀₉ which receives the output of the OR gate OR₈₅through an OR gate OR₈₇ is enabled. If the bass pattern signal T₁, T₂,T₄, T₈ is "1110", the AND gate A₁₁₁ which receives the output of the ORgate OR₈₅ is enabled. If the bass pattern signal T₁, T₂, T₄, T₈ is"0001", the AND gate 113 which receives the bass pattern signal only isenabled.

The outputs of the AND gates A₁₀₀ through A₁₁₃ are applied to an encoder56 consisting of OR gates OR₇₈ through OR₈₂. The encoder 56 produces thesubordinate note forming data SD₁ -SD₄ in accordance with the outputs ofthe AND gate A₁₀₀ through A₁₁₃.

The following Tables 7, 8, 9 and 10 show relations between the basspattern signal T₁, T₂, T₄, T₈ and the subordinate note forming data SD₁-SD₅ generated in response to the bass pattern signal in cases where nosignal is stored in any of the chord memories 55-1 through 55-3, i.e.,the detected chord is the major chord, where the seventh chord isdetected by existence of the seventh detection signal D₇ in the chordmemory 55-1 only, where the minor chord is detected by existence of theminor chord is detected by existence of the minor detection signal Dm inthe chord memory 55-2 only, and where the diminishment detection signalDd is stored in the chord memory 55-3 and the seventh detection signalD₇ and the minor detection signal Dm are stored in the chord memories55-1 and 55-2.

                  TABLE 7                                                         ______________________________________                                        The case where the major chord has been detected.                             T.sub.8                                                                            T.sub.4                                                                              T.sub.2                                                                              T.sub.1                                                                            SD.sub.5                                                                            SD.sub.4                                                                            SD.sub.3                                                                            SD.sub.2                                                                            SD.sub.1                      ______________________________________                                        0    0      0      0          0     0     0     0                             0    0      0      1          0     1     0     1                             0    0      1      0          1     0     0     1                             0    0      1      1          1     1     0     0                             0    1      0      0          1     0     1     0                             0    1      0      1          1     1     0     1                             0    1      1      0          1     1     1     0                             0    1      1      1          1     1     1     0                             1    0      0      0    1     0     0     0     0                             ______________________________________                                    

                  TABLE 8                                                         ______________________________________                                        The case where the major chord has been detected                              T.sub.8                                                                            T.sub.4                                                                              T.sub.2                                                                              T.sub.1                                                                            SD.sub.5                                                                            SD.sub.4                                                                            SD.sub.3                                                                            SD.sub.2                                                                            SD.sub.1                      ______________________________________                                        0    0      0      0          0     0     0     0                             0    0      0      1          0     1     0     1                             0    0      1      0          1     0     0     1                             0    0      1      1          1     1     0     0                             0    1      0      0          1     1     0     0                             0    1      0      1          1     1     0     1                             0    1      1      0          1     1     0     1                             0    1      1      1          1     1     0     1                             1    0      0      0    1     0     0     0     0                             ______________________________________                                    

                  TABLE 9                                                         ______________________________________                                        The case where the minor chord has been detected                              T.sub.8                                                                            T.sub.4                                                                              T.sub.2                                                                              T.sub.1                                                                            SD.sub.5                                                                            SD.sub.4                                                                            SD.sub.3                                                                            SD.sub.2                                                                            SD.sub.1                      ______________________________________                                        0    0      0      0          0     0     0     0                             0    0      0      1          0     1     0     1                             0    0      1      0          1     0     0     1                             0    0      1      1          1     1     0     0                             0    1      0      0          1     0     1     0                             0    1      0      1          1     1     0     1                             0    1      1      0          1     1     1     0                             0    1      1      1          1     1     1     0                             1    0      0      0    1     0     0     0     0                             ______________________________________                                    

                  TABLE 10                                                        ______________________________________                                        The case where the diminishment chord has been detected                       T.sub.8                                                                            T.sub.4                                                                              T.sub.2                                                                              T.sub.1                                                                            SD.sub.5                                                                            SD.sub.4                                                                            SD.sub.3                                                                            SD.sub.2                                                                            SD.sub.1                      ______________________________________                                        0    0      0      0          0     0     0     0                             0    0      0      1          0     1     0     0                             0    0      1      0          1     0     0     1                             0    0      1      1          1     1     0     0                             0    1      0      0          1     0     1     0                             0    1      0      1          1     1     0     1                             0    1      1      0          1     1     0     1                             0    1      1      1          1     1     1     0                             1    0      0      0    1     0     0     0     0                             ______________________________________                                    

The signals SD₁ through SD₄ among the subordinate note forming data SD₁-SD₅ generated by the subordinate note forming data generation circuit13 are applied to the inputs B of the adders 12-1 through 12-4 (FIG.11). The subordinate note forming data SD₁ -SD₄ represents, as haspreviously been described, a predetermined note interval and relationsbetween various note intervals and the subordinate note forming data SD₁-SD₄ are shown in the following Table 11. It should be noted, however,that signals representing prime, major second, major third and perfectfourth among the subordinate note forming data shown in Table 11 are notused in the present embodiment of the invention.

                  TABLE 11                                                        ______________________________________                                                    Subordinate note forming data                                     Note interval SD.sub.4 SD.sub.3                                                                              SD.sub.2                                                                            SD.sub.1                                 ______________________________________                                        Prime (1)     0        0       0     0                                        Minor second (2♭)                                                                0        0       0     1                                        Major second (2)                                                                            0        0       1     0                                        Minor third (3♭)                                                                 0        1       0     0                                        Major third (3)                                                                             0        1       0     1                                        Perfect fourth (4)                                                                          0        1       1     0                                        Diminished fifth (5♭)                                                            1        0       0     0                                        Perfect fifth (5)                                                                           1        0       0     1                                        Minor sixth (6♭)                                                                 1        0       1     0                                        Major sixth (6)                                                                             1        1       0     0                                        Minor seventh (7♭)                                                               1        1       0     1                                        Major seventh (7)                                                                           1        1       1     0                                        ______________________________________                                    

The adders 12-1 through 12-4 add the note code NC₁ -NC₄ representing theroot note applied to the inputs A with the subordinate note forming dataSD₁ -SD₄ applied to the inputs B to form a signal indicating a note nameof a desired subordinate note.

Values of the note code NC₁ -NC₄ representing the root note do notassume continuously increasing values as will be understood from Table5. With reference to Table 5, a code "0000" is missing before the notecode "0001" representing the note C♯, a code "0100" is missing betweenthe note code "0011" representing the note D♯ and the note code "0101"representing the note E, a code "1000" is missing between the note code"0111" representing the note F♯ and the note code "1001" representingthe note G and a code "1100" is missing between the note code "1011"representing the note A and the note code "1101" representing the noteA♯. The code "1100" among these missing codes is used as a note coderepresenting the note C_(L) on the lower tone side. Accordingly,contents of the note code NC₁ -NC₄ are rewritten as the following Table12.

                  TABLE 12                                                        ______________________________________                                                 Note code                                                            Note       NC.sub.4 NC.sub.3 NC.sub.2                                                                              NC.sub.1                                 ______________________________________                                        C♯                                                                           0        0        0       1                                        D          0        0        1       0                                        D♯                                                                           0        0        1       1                                        E          0        1        0       1                                        F          0        1        1       0                                        F♯                                                                           0        1        1       1                                        G          1        0        0       1                                        G♯                                                                           1        0        1       0                                        A          1        0        1       1                                        A♯                                                                           1        1        0       1                                        B          1        1        1       0                                        C          1        1        1       1                                        ______________________________________                                    

The values of the note code NC₁ -NC₄ are determined in the manner shownin Table 12 so that the subordinate notes may be easily formed by usingthe 4-bit note code NC₁ -NC₄ in the form of a circulating signal. If,however, a result of addition of the note code NC₁ -NC₄ and thesubordinate note forming data SD₁ -SD₄ becomes a code "0000", "0100","1000" or "1100" which is not used for the note code, a subordinate notecannot be formed. Accordingly, values of 2 bits NC₁ and NC₂ countingfrom the least significant bit are suitably corrected in accordance withthe first bit signal SD₁ or the second bit signal SD₂ of the subordinatenote forming data.

This correction of values is made by using the AND gates A₈₆, A₈₇ andA₈₈. The AND gate A₈₆ receives the first bit signal SD₁ of thesubordinate note forming data, the first bit NC₁ of the note code NC₁-NC₄ and the second bit NC₂ of the note code NC₁ -NC₄ which is theoutput of the OR gate OR₇₂. The AND gate A₈₇ receives the second bitsignal SD₂ of the subordinate note forming data, the output signal NC₁of OR gate OR₆₅ and the output signal NC₂ of the OR gate OR₇₂. The ANDgate A₈₈ receives the second bit signal SD₂ of the subordinate noteforming data and a signal produced by inverting the first bit NC₁ of thenote code NC₁ -NC₄ which is the output of the OR gate OR₇₁ by aninverter I₄₅ and the output signal NC₂ of the OR gate OR₇₂. Accordingly,if either one of logical formulas

    NC.sub.1.NC.sub.2.SD.sub.1                                 (5)

    NC.sub.1.NC.sub.2.SD.sub.2                                 (6)

    NC.sub.1.NC.sub.2.SD.sub.3                                 (7)

is satisfied, a signal "1" is applied to a carry input Ci of the adder12-1 through an OR gate OR₇₀ to add "1" to the contents of the adder12-1.

If, for example, the note code NC₄ -NC₁ "0011" representing the note Dand the subordinate note forming data "0101" representing the majorthird degree are added together, a value "1000" is obtained and thisvalue "1000" is note used as the note code NC₄ -NC₁. At this time,however, the AND gate A₈₆ is enabled to add "1" to the result ofaddition "1000" thereby producing a note code NC₄ -NC₁ "1001". In thismanner, when the result of addition has become a code which is not usedas the note code NC₄ -NC₁ or a code "1100", a value "1" is added to theresult of addition for correction of the value of the result ofaddition.

A carry signal generated by the adder 14-4 when the result of additionhas exceeded "1111" is applied to the adder 12-5 through the AND gateA₉₁ which has been enabled by the output "1" of the above described ANDgate A₈₅.

The signal SD₅ among the subordinate note forming data SD₁ -SD₅ isapplied to the inputs A of the adders 12-5 and 12-6 through a NOR gateNR₇ and an OR gate OR₇₃. If the signal SD₅ which represents a noteinterval of one octave is "1", the octave data B₁ -B₃ produced by thedealy flip-flops DF₄₄ through DF₄₆ is raised by one octave. If thesignal SD₅ is "0", signals "1" and 37 0" are applied to the inputs A ofthe adders 12-5 and 12-6 in response to the octave code OC₁, OC₂ fromthe key code registers 9-5 and 9-6 and the delay flip-flops DF₄₄ throughDF₄₆ produce the octave data B₁ -B₃ representing the first octave. Ifthe signal SD₅ is turned to "1" in this state, signals "0" and "1" arerespectively applied to the inputs A of the adders 12-5 and 12-6 and thedelay flip-flops DF₄₄ through DF₄₆ produce the octave data B₁ -B₃representing the second octave which is one octave higher than the firstoctave.

If a predetermined chord has been formed by notes of keys depressed inthe lower keyboard and this chord thereafter is broken by change in thedepressed keys, the root note of the broken chord is used again. When apredetermined chord has been formed by the notes of the keys depressedin the lower keyboard, the AND gate A₃₇ (FIG. 8) of the control signalforming circuit 11 is enabled to provide a signal "1" to the memory 39thorugh the OR gate OR₃₉ 39. The memory 39 thus stores a signal "1".

If keys depressed in the lower keyboard have been changed and the chordhas been broken, the output NCH of the memory 36 (FIG. 9) is turned to"1" and this signal "1" is applied to an AND gate A₃₂ of the controlsignal forming circuit 11 (FIG. 8). The AND gate A₃₂ receives at theother input thereof a signal produced by inverting the output CHH of thechord detection signal memory 37 by an inverter I₂₃ and the output ofthe memory 39. The AND gate A₃₂ therefore is enabled and a signal "1" isapplied to an AND gate A₄₁. The AND gate A₄₁ thereby outputs a signal"1" and this signal "1" is applied to a delay flip-flop DF₃₂ through ORgates OR₄₁ and OR₅₇. The output of the delay flip-flop DF₃₂ is appliedto the AND gate A₈₅ (FIG. 11) as the automatic bass chord data selectionsignal AKD, whereby a subordinate note forming operation is performed inthe same manner as was previously described.

An AND gate A₄₀ is enabled during the last 48 microseconds of the signalA₁ T and a signal "1" is applied to the AND gate A₇₆ of the memory 39through the NOR gate NR₈ thereby clearing the signal stored in thememory 39. To the AND gate A₇₆ of the memory 39 are also applied,through the NOR gate NR₂ and line 36, the outputs of AND gates A₆₃, A₆₄and A₆₅ which are enabled upon receipt of the output signals of therespective AND gates A₆₂ of the function data memories 6-1 through 6-3(FIG. 10) and signal produced by inverting the outputs of the delayflip-flops DF₂₅ by inverters I₃₄, I₃₅ and I₃₆. Accordingly, the memory39 is cleared by turnign on of either the function switch selecting thesingle finger function, the one selecting the finger chord function orthe one selecting the custom function.

If the function switch selecting the memory function is turned on andthe signal M thereby is stored in the function data memory 6-4 (FIG.10), this signal is applied to an AND gate A₆₆. The AND gate A₆₆receives at the other inputs thereof the output of the NOR gate NR₂ andthe output of an OR gate OR₅₂ to which are applied the signal CON fromthe function data memory 6-5 indicating that the constant function hasbeen selected and the signal RHY from the shift register 54 (FIG. 12)indicating that the rhythm is on. The AND gate A₆₆ therefore is enabledand produces a memory signal MM if the constant function has beenselected or the rhythm is on. The signal MM is applied to the signalhold AND gate A₇₅ of the memory 38 (FIG. 8). The root note load signalLKM is also applied to a delay flip-flop DF₃₄ of the memory 38 throughan OR gate OR₅₉. Accordingly, the memory 38 stores a signal "1" if theroot note load signal LKN is produced when the memory signal MM ispresent.

The output M' of the memory 38 is applied to an AND gate A₄₂. The ANDgate A₄₂ receives at the other input thereof a signal produced byinverting the output NCH of the non-chord signal memory 36 by aninverter I₂₂. Conditions for enabling the AND gate A₄₂ are expressed bythe following logical formula (8):

    FC.M'.A.sub.1 T.TTP.NCH                                    (8)

Accordingly, the AND gate A₄₂ is enabled after release of the depressedkey and supplies a signal "1" to the delay flip-flop DF₃₂ through the ORgates OR₄₁ and OR₅₇ for producing the automatic bass chord dataselection signal AKD. Consequently, by turning on of the function switchselecting the memory function, the automatic bass chord key code data isgenerated even after the release of the depressed key in accordance withthe root note detected on the basis of the note of the depressed key.

In the event that the key depressed in the lower keyboard has beenreleased or a different key has newly been depressed with resultingchange in the root note, generation of the subordinate note forming data₁ -SD₅ is inhibited in the following manner. Signals applied to the datainputs of delay flip-flops DF₃₇ of the key code registers 9-1 through9-4 (FIG. 11) and output signals of the delay flip-flops DF₃₇ areapplied to exclusive OR gates ER₁ through ER₄. The outputs of theexclusive OR gates ER₁ through ER₄ in turn are applied to the OR gateOR₇₆ (FIG. 12) through the OR gate OR₆₃. The output of the OR gate OR₇₆is inverted by the inverter I₄₇ and thereafter is applied to the ANDgate A₁₂₂. Accordingly, change in the signal applied to the delayflip-flops DF₃₇ of the key code registers 9-1 through 9-4 causes anoutput "1" to be produced by any one of the exclusive OR gates ER₁through ER₄. This disables the AND gate A₁₂₂ and, accodingly, generationof the subordinate note data SD₁ -SD₅ is inhibited.

An OR gate OR₆₃ also receives the signal CON selecting the constantfunction stored in the function data memory 6-5 (FIG. 10) and a signalproduced by inverting the automatic base chord data selection signal AKDby an inverter I₄₂. Accordingly, generation of the subordinate noteforming data SD₁ -SD₅ is likewise inhibited when the constant functionhas been selected or the automatic bass chord data selection signal AKDhas not been produced.

GENERATION OF THE KEY CODE DATA IN CASE THE CUSTOM FUNCTION HAS BEENSELECTED

If the custom function has been selected, the automatic chordperformance is made in accordance with notes of plural keys depressed inthe lower keyboard and the automatic bass chord performance is made inaccordance with a note of a single key depressed in the pedal keyboard.More specifically, the key code data for performing the automatic chordis generated in accordance with signals from the key switches beingactually depressed in the lower keyboard in the same manner as in thecase where the finger chord has been selected. On the other hand, thekey code data for performing the automatic bass is generated in thefollowing manner in accordance with a type of chord formed by the notesof the plural keys depressed in the lower keyboard and utilizing thenote of the single key depressed in the pedal keyboard as a root note.

As the block P including the key switch of the pedal keyboard has beenextracted by the block detection circuit 2 (FIG. 4) and the signal PThas been outputted from the AND gate A₂₆ of the decoder 10 (FIG. 8),this signal is applied as the root note load signal LKN to the key coderegisters 9-1 through 9-4 through the AND gate A₃₅ and the OR gate OR₃₈causing the note code signal NC₁ -NC₄ representing the note of the keydepressed in the pedal keyboard to be loaded in delay flip-flops DF₃₇ ofthe key code registers 9-1 through 9-4.

In the meanwhile, if the notes of the keys being depressed in the lowerkeyboard have formed a chord, the sinals D₇, D_(m) and D_(d) aregenerated in accordance with a type of the chord detected by the chorddetection circuit 5 (FIG. 9). The signals D₇, D_(m) and D_(d) are storedin corresponding chord memories 55-1 through 55-3 of the subordinatenote forming data generation circuit 13 (FIG. 12).

The subordinate note forming data SD₁ -SD₅ is produced by thesubordinate note forming data generation circuit 13 (FIG. 13) inaccordance with the signals D₇, D_(m) and D_(d) representing the type ofthe chord stored in the chord memories 55-1 through 55-3 and the basspattern signal T₁, T₂, T₄, T₈ outputted by the shift register 54. Thesubordinate note forming data SD₁ -SD₅ is applied to the adders 12-1through 12-6 (FIG. 11) to form desired subordinate note signals inaccordance with the root note loaded in the key code registers 9-1through 9-4. This operation is the same as in the case where the fingerchord function has been selected.

If the memory function has been selected and the memory signal MM isbeing provided by the AND gate A₆₆ (FIG. 10), the key code data KC isgenerated with a note of a key which was depressed in the pedal keyboardbeing utilized as a root note even after the depressed key has beenreleased. If a key is depressed in the pedal keyboard, the AND gate A₃₅(FIG. 8) is enabled and the note code NC₄ -NC₁ representing the note ofthe depressed key is loaded in the delay flip-flops DF₃₇ of the key coderegisters 9-1 through 9-4. The output "1" of the AND gate A₃₅ is alsoapplied to the memory 39 and stored therein through the OR gate OR₃₉. Ifthe memory signal MM is present at this time, the AND gate A₃₅ isenabled to cause the root note load signal LKN to be outputted from theOR gate OR₃₈ and a signal "1" to be stored in the memory 38.

During the last 48 microseconds of the signal A₁ T the AND gate A₃₉ isenabled and a signal "1" is inverted by a NOR gate NR₈ and thereafter isapplied to the AND gate A₇₆ of the memory 39 to clear the storage of thememory 39. Accordingly, if the key depressed in the pedal keyboard isreleased, the output of the memory 39 is turned to "0". This signal isinverted by the inverter I₂₁ and thereafter is applied to an AND gateA₄₃. The AND gate A₄₃ receives at the other inputs thereof the outputsignal M' of the memory 38, the signal TTP, the signal CA and the signalA₁ T. Conditions for enabling the AND gate A₄₃ are expressed by thefollowing logical formula (9):

    Ca.M'.A.sub.1 T.TTP.Q'                                     (9)

In the above formula (9), Q' designates a signal produced by invertingthe output of the memory 39.

Accordingly, the AND gate A₄₃ is enabled to apply a signal "1" to adelay flip-flop DF₃₂ through the DR gates OR₄₁ and OR₅₇. The delayflip-flop DF₃₂ thereupon produces the automatic bass chord dataselection signal AKD and the subordinate note forming operation isperformed in the same manner as has previously been described with thenote of the key which was being depressed in the pedal keyboard beforethe release of the key being utilized as a root note.

GENERATION OF THE KEY CODE DATA IN CASE THE SINGLE FINGER FUNCTION HASBEEN SELECTED

If the single finger function has been slected, the key code datarepresenting chord notes for performing the automatic chord and the keycode data representing the chord notes for performing the automatic bassare produced in accordance with a note of a single key depressed in thelower keyboard.

Since the key depressed in the plower keyboard is only one in theautomatic bass chord performance according to the single fingerfunction, a type of chord cannot be detected. Accordingly, anarrangement is made so that a type of chord can be indicated bydepressing a white key or a block key in the pedal keyboard. Morespecifically, depression of a white key in the pedal keyboard designatesa chord including a minor seventh degree note 7 (i.e. seventh chord),whereas depression of a block key designates a chord including a minorthird degree note 3 (i.e. minor chord). If neither a white key nor ablack key is depressed, that designates a major chord.

If a white key or a black key is depressed in the pedal keyboard, thesignal PT is produced by the AND gate A₂₆ of the decoder 10 (FIG. 8).This signal PT is applied to an AND gate A₃₃. The AND gate A₃₃ receivesat the other input thereof the signal SF indicating that the singlefinger function has been selected. The AND gate A₃₃ therefore is enabledto apply a signal PT.SF to AND gates A₅₆ and A₅₇ of the chord detectioncircuit 5 (FIG. 9). To the other input of the AND gate A₅₆ are appliedthorugh an OR gate OR₄₆ signals on the lines 21, 23, 25, 26, 28, 30, 32and 33 of the note detection circuit 4 corresponding to the key switchesof the white keys. To the other input of the AND gate A₅₇ are appliedthrough an OR gate OR₄₇ signals on the output lines 22, 24, 27, 29, 31corresponding to the key switches of the black keys. If, accordingly, awhite key is depressed in the pedal keyboard, the AND gate A₅₆ isenabled and a signal "1" is outputted as the seventh detection signal D₇through the OR gate OR₄₆. If a black key is depressed in the pedalkeyboard, the AND gate A₅₇ is enabled and a signal "1" is outputted asthe minor detection signal D_(m) through the OR gate OR₄₉.

The seventh detectection signal D₇ and the minor detection signal D_(m)are applied to the chord memories 55-1 and 55-2 shown in FIG. 12 andstored therein.

If neither white key nor a black key is depressed in the pedal keyboard,the AND gates A₅₆ and A₅₇ are not enabled so that no signal is stored inthe chord memories 55-1 and 55-2. This state represents that the majorchord has been designated.

As the non-chord signal NC is outputted from the chord detection circuit5 (FIG. 9), the AND gate A₃₈ is enabled and the root note load signalLKN is outputted from the OR gate OR₃₈, thereby causing the note codeNC₁ -NC₄ representing a note of a single key being depressed in thelower keyboard to be loaded as a signal representing a root note in thedelay flip-flop DF₃₇ of the key code registers 9-1 through 9-4 (FIG.11).

The automatic bass performance key code data in the case where thesingle finger function has been selected is produced by applying theoutput signals of the chord memories 55-1 and 55-2 and the subordinatenote forming data SD₁ -SD₅ generated in response to the bass patternsignal T₁, T₂, T₄, T₈ from the shift register 54 to the adders 12-1through 12-5 (FIG. 11) and thereby processing the note code NC₁ -NC₄representing the root note stored in the key code registers 9-1 through9-4. The operations of the subordinate note forming data generationcircuit 13 and the adders 12-1 through 12-6 are the same as those in thecase where the finger chord function or the custom function has beenselected. In the case of the single finger function, however, the signalDd representing the diminishment chord is not used.

In the case where the single finger function has been selected, only onekey is depressed in the lower keyboard and, accordingly, key code datafor the automatic chord performance cannot be produced on the basis ofthe signal from the key switch for the single depressed key.Accordingly, the key code data for the automatic bass chord performancein the case of the single finger function mode is generated byprocessing a root note by the subordinate note forming data SD₁ -SD₄generated by the subordinate note data forming generation circuit 13(FIG. 12).

The signal SF from the function data memory 6-1 (FIG. 10) indicatingthat the single finger function has been selected is applied to an ANDgate A₉₆ shown in FIG. 12. The AND gate A₉₆ receives at the other inputthereof the automatic bass chord data selection signal AKD which is theoutput signal of the delay flip-flop DF₃₂ (FIG. 8). The AND gate A₉₆therefore is enabled upon receipt of the automatic bass chord dataselection signal AKD and applies a signal "1" to a shift register 58.The shift register 58 successively shifts a signal "1" and output asignal "1" from the outputs Q_(A) through Q_(c).

The subordinate note forming data SD₁ -SD₅ used for forming the key codedata for the automatic chord performance is generated in response to theoutput of the shift register 58 and the signals stored in the chordmemories 55-1 and 55-2.

Assume, for example, that a signal "1" is stored in the chord memory55-1 thereby designating the seventh dh chord. If in this case a signal"1" is delivered from the output Q_(A) of the shift register 58, thesubordinate note forming data SD₄ -SD₁ "0000" is generated. If a signal"1" is delivered from the output Q_(B) of the shift register 58, an ANDgate A₉₉ is enabled and the subordinate note forming data SD₄ -SD₁"0101" representing the major third degree note interval is generated.If a signal "1" is delivered from the output Q_(c) of the shift register58, an AND gate A₉₈ is enabled and the subordinate note forming data SD₄-SD₁ "1101" representing the minor seventh degree note interval isgenerated.

Relations between the output signals Q_(A), Q_(B) and and Q_(C) of theshift register 58 and the subordinate note forming data SD₁ -SD₄generated in response to these output signals in cases where a signal"1" is not stored in the chord memory 55-1 or 55-2 whereby the majorchord is designated, where a signal "1" is stored in the chordd memory55-2 whereby the major chord is designated and where a signal "1" isstored in the chord memry 55-1 whereby the seventh chord is designatedare shown in the following Tables 13, 14 and 15:

                  TABLE 13                                                        ______________________________________                                        In case the major chord has been designated                                           SD.sub.4                                                                             SD.sub.3  SD.sub.2  SD.sub.1                                   ______________________________________                                        Q.sub.A   0        0         0       0                                        Q.sub.B   0        1         0       1                                        Q.sub.C   1        0         0       1                                        ______________________________________                                    

                  TABLE 14                                                        ______________________________________                                        In case the minor chord has been designated                                           SD.sub.4                                                                             SD.sub.3  SD.sub.2  SD.sub.1                                   ______________________________________                                        Q.sub.A   0        0         0       0                                        Q.sub.B   0        1         0       0                                        Q.sub.C   1        0         0       1                                        ______________________________________                                    

                  TABLE 15                                                        ______________________________________                                        In case the seventh chord has been designated                                         SD.sub.4                                                                             SD.sub.3  SD.sub.2  SD.sub.1                                   ______________________________________                                        Q.sub.A   0        0         0       0                                        Q.sub.B   0        1         0       1                                        Q.sub.C   1        1         0       1                                        ______________________________________                                    

If the signal "1" is produced from the outputs Q_(A) through Q_(C) ofthe shift register 58, an OR gate OR₇₇ produces a signal T_(CH). Thissignal T_(CH) is applied to the AND gates A₈₁ through A₈₄ through the ORgate OR₆₄. The AND gates A₈₁ through A₈₄ are thereby enabled to applythe note code NC₁ -NC₄ representing the root note and stored in the keycode registers 9-1 through 9-4 to the inputs A of the adders 12-1through 12-4.

To the inputs B of the adders 12-1 through 12-4 are applied thesubordinate note forming data SD₁ -SD₄. By adding the note code NC₁ -NC₄representing the root note and the subordinate notefforming data SD₁-SD₄ together, note data N₁ -N₄ for the automatic chord erformance isproduced. This note data N₁ -N₄ is delivered out through delayflip-flops DF₄₀ through DF₄₃. The operation for forming of the note dataN₁ -N₄ is substantially the same as the one for forming the automaticbass performance key code data.

The signal T_(CH) produced by the OR gate OR₇₇ is applied to an OR gateOR₂₈ (FIG. 8) to produce the signal L representing a chord note (a notein the lower keyboard). This signal T_(CH) is also supplied to theinputs A of the adders 12-5 and 12-6 through the NOR gate NR₇ and the ORgate OR₇₃ shown in FIG. 11. The output of the adder 12-5 thereupon isturned to "0" and the output of the adder 12-6 is turned to "1" wherebythe octave data B₁ -B₃ representing the second octave is provided by thedelay flip-flops DF₄₄ through DF₄₆.

If the memory function has been selected, the key code data KCrepresenting the chord tones for the automatic chord performance and thekey code data KC representing the bass tone for the automatic bassperformance are generated using the note of the depressed key in thelower keyboard as a root note even after the depressed key has beenreleased. If the function siwtch for selecting the memory function hasbeen turned on, the memory signal MM outputted from the AND gate A₆₆(FIG. 10) is applied to the AND gate A₇₅ of the memory 38 (FIG. 8).Accordingly, a signal "1" is stored in the memory 38 simultaneously withoutputting of the root note load signal LKN from the OR gate OR₃₈. Theoutput M' of the memory 38 is applied to an AND gate A₄₄. The AND gateA₄₄ receives at the other inputs thereof a signal NCH produced byinverting the output NCH of the non-chord memory 36 by the inverter I₂₂,the signal TTP, the signal SF and the signal A₁ T. Conditions forenabling the AND gate A₄₄ are expressed by the following logical formula(9):

    NCH.M'.TTP.SF.A.sub.1 T                                    (9)

Accordingly, the AND gate A₄₄ is enabled after release of the keydepressed in the lower keyboard to apply a signal "1" to the delayflip-flop DF₃₂ through the OR gates OR₄₁ and OR₅₇. This causes the delayflip-flop DF₃₂ to produce the automatic bass chord data selection signalAKD whereby the key code data representing the chord tones for theautomatic chord performance and the key code data representing the chordtones for the automatic chord performance and the key code datarepresenting the bass tones for the autoamtic bass performance aregenerated using the note of the key being depressed in the lowerkeyboard before release of the key as the root note.

GENERATION OF A CHORD TONE SOUNDING TIMING SIGNAL ETC.

A chord tone sounding timing signal CG which designates timing ofsounding of a chord tone (a tone of the lower keyboard) is generated inresponse to the signal T_(C) outputted by the shift register 54 (FIG.12). The signal T_(C) outputted by the shift register 54 is applied toan AND gate A₁₁₇. To another input of the AND gate A₁₁₇ is applied theautomatic bass chord selection signal ABC which is outputted by the ORgate OR₅₃ (FIG. 10). This signal ABC is a signal which becomes "1" whenonly one of the signal SF for selecting the single finger function, thesignal FC for selecting the finger chord function and the signal CA forselecting the custom function has been produced, i.e., when any one ofthe automatic bass chord functions has been selected. Accordingly, whenany one of the automatic bass chord functions has been selected, the ANDgate A₁₁₇ is enabled to deliver out the signal T_(C) as the chord tonesounding timing signal CG.

A normal gate signal NG is employed for adjusting the level of a musicaltone depending upon whether the automatic bass chord is performed or thenormal performance is made. If a key is depressed in the lower keyboard,or a key is depressed in the pedal keyboard when neither the singlefinger function, finger chord function nor the custom function has beenselected, or a key is depressed in the pedal keyboard when the customfunction has been selected, a signal "1" is outputted by the OR gateOR₃₇ (FIG. 8) and applied to the memory 370. The memory 370 stores thissignal "1" by applying it to the delay flip-flop DF₃₃ through the ORgate OR₅₈ the output signal of which is fed back to the input thereofthrough the AND gate A₇₄ and the OR gate OR₅₈.

The output of the memory 370 is applied to an AND gate A₁₁₉ (FIG. 12) asthe key-on signal KON. The AND gate A₁₁₉ receives at other inputsthereof the output of an AND gate A₁₁₆ which is enabled when the basspattern signal T₈, T₄, T₂, T₁ delivered from the shift register 54 is"1111" (indicating that no rhythm has been selected), the constantsignal CON and a signal produced by inverting the signal ABC by aninverter I₄₈ through an OR gate OR₉₀.

Accordingly, the AND gate A₁₁₉ is enabled when any one of the output ofthe AND gate A₁₁₆, the constant signal CON and the output of theinverter I₄₈ is "1" and a signal "1" is applied to a delay flip-flopDF₅₀ through an OR gate OR₉₁. The output signal of the delay flip-flopDF₅₀ is fed back to the input thereof through an AND gate A₁₁₈ and theOR gate OR₉₁. The AND gate A₁₁₈ receives at another input thereof theoutputs of the OR gate OR₉₀. By this arrangement, the signal applied tothe delay flip-flop DF₅₀ is held therein so long as the output of the ORgate OR₉₀ is "1". The output NG of the delay flip-flop DF₅₀ is invertedby an inverter I₅₉ and thereafter is delivered from a terminal T_(NG) asa signal NG.

To the AND gate A₇₄ of the memory 370 (FIG. 8) outputting the key-onsignal KON is applied a signal produced by inverting the output signalLF₁ of the delay flip-flop DF₃₀ by an inverter I₆₂ so that the signalstored in the memory 370 is cleared each time the signal LF₁ isproduced.

If a signal T₀ is produced by the shift register 54 when the constantsignal CON is present, an AND gate 115 is enabled and the subordinatenote forming data SD₅ is thereby turned to "1" resulting in rise of thekey code data KC by one octave. If the signal T₀ is produced when thebass pattern signal T₈ is "1", an AND gate A₁₁₄ is enabled. In this casealso the subordinate note forming data SD₅ is turned to "1" and the keycode data KC is raised by one octave.

The constant signal CON and the output of the AND gate A₁₁₆ aredelivered as a signal CON' through an OR gate OR₈₉. This signal CON' isused for continuously producing the chord tone instead of producing itintermittently at a timing of the chord tone sounding timing signal CG.

What is claimed is:
 1. A key code data generator comprising:a switchmatrix circuit including a plurality of key switches assigned torespective notes and connected between row lines and column lines, saidrow lines defining respective blocks of the key switches and said columnlines defining respective notes of the key switches in each said block;a block detection circuit connected to said switch matrix circuit fordetecting all row lines to which key switches in operation areconnected; a note detection circuit connected to said switch matrixcircuit for detecting all column lines connected with a single one ofsaid detected row lines via the key switches in operation, anddelivering note codes representing said detected row lines one afteranother in a time shared fashion, the column line detection beingcarried out for one row line after another for each of said row linesdetected; a control circuit connected to said block detection circuitand said note detection circuit for causing said row line detection in afirst period of time and said column line detection in a second periodof time; a circuit connection for causing said note detection circuit todeliver in a third period of time all the note codes available one afteranother; a chord detection circuit including a shift register connectedto said note detection circuit and having stages for storing the stateof said column lines detected with respect to predetermined row lines insaid second period, contents of said stages being circulatingly shiftedin synchronism with said time shared delivery of the note codes fromsaid note detection circuit in said third period, and a chord typedetecting logic connected to said stages for detecting establishment ofone of predetermined types of chord; and a code register for storing thenote code delivered from said note detection circuit at the moment saidchord type detecting logic detects said establishment, the registerednote code representing the root note of the detected chord.
 2. A keycode data generator as defined in claim 1 whereinsaid circuit connectionfurther causes said note detection circuit to deliver in a fourth periodof time all the note codes available one after another; the contents ofsaid stages of said chord detection circuit are circulatingly shifted insynchronism with the time shared delivery of said note codes in saidfourth period; said chord detection circuit further comprises apreferential detection network connected to a predetermined one of saidstages for detecting only if said chord type detecting logic has notdetected any establishment of a chord, a first arrival of the shiftedcontents at said predetermined one stage in said fourth period; and saidcode register stores the note code delivered from said note detectioncircuit at the moment said preferential detection network detects saidarrival, the registered note code representing a note to be used as aroot note for performing a chord.
 3. A key code data generator asdefined in claim 2 which further comprises:a data generation circuitconnected to said chord detection circuit for generating, upon detectionof said establishment of a type of chord, data for forming subordinatenotes which are appropriate for the detected type of chord; and aprocessing circuit connected to said code register and to said datageneration circuit for processing said registered note code and saiddata and producing key codes which designate a root note and subordinatenotes for a chord to be performed as an automatic bass chordperformance.
 4. A key code data generator as defined in claim 1wherein:said switch matrix circuit further includes at least one furtherrow lines in addition to said row lines which are connected with saidkey switches, and a plurality of function switches assigned torespective performance functions to be selectively rendered andconnected between said at least one further row lines and said columnlines, said at least one further row lines defining blocks of thefunction switches and being connected to said block detection circuit;said block detection circuit and said note detection circuit furtherdetect function switches in operation; and said key code data generatorfurther comprising: a function data memory connected to said notedetection circuit for storing the detected states of said functionswitches while the blocks including the function switches are beingdetected, and for delivering corresponding function data; and enablingmeans, connected to said function data memory, for enabling said circuitconnection, said chord detection circuit and said code register tooperate in the designated function in response to delivery of certainfunction data.
 5. A key code data generator as defined in claim 1wherein:said note detection circuit includes a plurality of storagecells each corresponding to a respective note name in a musical scale,data representing detected column lines connected via key switches inoperation being entered into storage cells corresponding to the notenames of said operated key switches during said first period of time, anote encoder connected to said cells, said note encoder sequentiallyproducing, during said second period of time, the note codes for dataentered in said storage cells, said control circuit causing entry ofdata into all of said storage cells at the beginning of said thirdperiod of time, and causing sequential readout of said cells during saidthird period of time in synchronism with said circulating shifting ofsaid chord detection circuit, said note encoder thereby producing all ofthe note codes one after another.
 6. A key code data generator asdefined in claim 4 and contained in a single integrated circuit chip,said certain function data being used to control operations of othercircuits on said chip, together with function data transmission meansfor providing other delivered function data in serial format to anoutput terminal of said chip for use by circuitry external to said chip.7. In combination with an electronic musical instrument having a noteselection keyboard and switches for the selection of performancefunctions, a key code data generator comprising:a note detection circuitoperatively connected to said keyboard and to said switches and having aset of storage cells, individual storage cells being assigned both to arespective note name in a musical octave and to a specified performancefunction, and an encoder directly connected to said set of storage cellsfor providing note codes identifying the cells containing data, a chorddetection register having a separate stage corresponding to each notename, and associated chord detection logic for detecting chord types bythe relative position of data in said stages, and control signalformation means for providing sequential first, second and third sets ofcontrol signals which operate said note detection circuit sequentiallyin:a first mode in which said first set of control signals causes dataindicative of selected function switches to be entered into ones of saidstorage cells assigned to the corresponding functions, said encoder thenproviding note codes representing said selected performance functions, asecond mode in which said second set of control signals causes datarepresenting keys selected on said keyboard to be entered into storagecells assigned to note names corresponding to the selected keys, saidencoder then providing note codes representing selected notes, saidselected key representing data also being entered into correspondingstages in said chord detection register in the event that, during saidfirst mode, the note code for a certain selected performance functionwas provided, and a third mode, enabled by provision during said firstmode of said note code for a certain selected function, wherein saidthird set of control signals causes said chord detection register to berecirculatingly shifted in synchronism with successive provision by saidencoder of note codes for each of said storage cells, detection of achord by said detection logic causing said control signal formationmeans to generate a signal which gates the note code concurrentlyprovided by said encoder to a key code register, said gated note codeidentifying the root note of said chord.
 8. On a single integratedcircuit chip intended for use in an electronic musical instrument of thetype having note selection keys and performance function selectionswitches, said keys and said switches being arranged in blocks connectedto said chip by common block lines:first circuit means for scanning eachblock of performance function switches to detect operated switches andto produce corresponding performance function designating codes forcontrol of circuitry on said chip, and first output means for externallydelivering said performance designation codes only to said instrumentvia an output terminal on said chip, chord detection circuitry on saidchip, a second circuit means for scanning each block of keys to detectdepressed keys and, in response to production by said first circuitmeans of certain codes designating specific automatic performancefunctions, to supply data representing detected depressed keys to saidchord detection circuitry a second output means for supplying to saidinstrument, via a separate output port on said chip, multibit note codesrepresenting detected depressed keys detected by said second circuitmeans, and third circuit means, enabled by production by said firstcircuit means of said certain automatic performance function designatingcodes and including said chord detection circuitry, for detecting thechord type and root note represented by said depressed keys, and forsupplying via said output port note codes, based on the detected chordtype and root note, for an automatic performance of the type designatedby said certain function designating codes.